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ds07-16504-2e fujitsu semiconductor data sheet 32-bit proprietary microcontroller cmos fr60 mb91350a series MB91F355A/mb91355a/mb91354a/mb91v350a description the fr families are lines of standard single-chip microc ontrollers each based on a 32-bit high-performance risc cpu, incorporating a variety of i/o resources and bus control features for embedded control applications which require high cpu performance for this fr60 family is based on fr30 and fr40 families an d enhanced is bus access. the fr60 family is a line of single-chip oriented microcontrollers incorporating a wealth of peripheral resources. the fr60 family is optimized for embedded control app lications requiring high processing power of the cpu, such as dvd player, navigation, high perf ormance fax machine, and printer controls. features 1. fr cpu ? 32-bit risc, load/store architecture with a five-stage pipeline maximum operating frequency: 50 mhz (using the pll at an os cillation frequency of 12.5 mhz) 16-bit fixed length instructions (basic instructions), 1 instruction per cycle instruction set optimized for embedded applications: memo ry-to-memory transfer, bit manipulation, barrel shift etc. instructions adapted for high-level la nguages: function entry/exit instructions , multiple-register load/store in- structions (continued) pac k ag e i 2 c license purchase of fujitsu i 2 c components conveys a li cense under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specificati on as defined by philips. 176-pin plastic lqfp (fpt-176p-m02)
mb91350a series 2 register interlock functions: facilitating coding in assemblers on-chip multiplier supported at the instruction level. signed 32-bit multiplication: 5 cycles. signed 16-bit multiplication: 3 cycles interrupt (pc, ps save): 6 cycles, 16 priority levels harvard architecture allowing program access and data access to be executed simultaneously fr family instruction compatible 2. bus interface maximum operating frequency: 25 mhz capable of up to 24-bit addres s full output (16 mb of space) 8,16-bit data output built-in pre-fetch buffer non-used data and address pin are usable as general i/o port. capable of chip-select signal outp ut for completely independent four areas settable in 64 kb minimum support for various memory interfaces: sram, rom/flash, page mode flash rom, page mode rom basic bus cycle: 2 cycles programmable automatic wait cycle generator c apable of inserting wait cycles for each area rdy input for external wait cycles support for fly-by transfer for dma, wh ich enables wait control of independent i/o 3. mounted memory 4. dmac (dma controller) capable of simultaneous operation of up to 5 channels (3 channels for external external operation) three transfer sources (external pin, internal peripheral, software) selectable by software. (transfer can be started from uart0/1/2.) addressing using 32-bit full addressing mode (increment, decrement, fixed) transfer modes (demand transfer, burst transfer, step transfer, block transfer) support for fly-by transfer (between external i/o and memory) selectable transfer data size: 8, 16, or 32-bit multi-byte transfer enabled (by software) dmac descriptor in io areas (200 h to 240 h , 1000 h to 1024 h ) 5. bit search module (for realos) search for the position of the bit 1/0- changed first in 1 word from the msb 6. various timers 4 channels of 16-bit reload timer (including 1 channel for realos): internal clock frequency selectable from among divisions by 2/8/32 (division by 64/128 selectable only for ch3) 16-bit free-running timer: 1 channel. output compare module: 8 channels. input capture module: 4 channels 16-bit ppg timer 6 channels 7. uart uart full duplex double buffer 5 channel selectable parity on/off asynchronous (start-stop synchronized) or clk-synchronous communications selectable (continued) memory mb91v350a MB91F355A mb91355a mb91354a rom no 512 kb 512 kb 384 kb ram (stack) 16 kb 16 kb 16 kb 8 kb ram (executable) 16 kb 8 kb 8 kb 8 kb
mb91350a series 3 (continued) internal timer for dedicated baud rate external clock can be used as transfer clock assorted error detection functions (for parity, frame, and overrun errors) 115 kbps support 8. sio 3 channels for 8-bit data serial transfer shift clock selectable from amo ng internal three and external one shift direction selectable (transfer from lsb or msb) selectable 9. interrupt controller total of 17 external interrupt lines (1 nonmaskable in terrupt pin and 16 normal interrupt pins available for wake up from stop) interrupt from internal peripheral programmable priorities (16 levels) for all interrupts except the non-maskable interrupt 10. d/a converter 8-bit resolution. 3 channels 11. a/d converter 10-bit resolution. 12 channels casting time for serial/parallel conversion: 1.48 s conversion mode (single conversion mode, continuous conversion mode) activation source (software, external trigger, peripheral interrupt) 12. other interval timer/counter 8/16-bit up/down counter 16-bit ppg timer 5 channels watch dog timer 13. i 2 c bus interface (400 kbps supported) 1channel master/slave sending and receiving arbitration and clock synchronization 14. i/o port 3 v i/o ports (16 ports shared for external interrupts support 5 v input.) max 126 ports 15. other features internal oscillator circuit as clock source, allowing pll multiplication to be selected provided with init as a reset pin (the cpu operates without os cillation stabilization wait interval when the init pin is reset.) others, watch-dog timer reset, software reset enable support for stop and sleep modes for low power consumption, capable of saving power during cpu operation at 32 khz. gear function built-in time base timer package: lqfp-176 (lead pitch: 0.50 mm) cmos technology(0.35 m) power supply voltage: 3.3 v 0.3 v
mb91350a series 4 pin assignment (top view) (fpt-176p-m02) 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 pg5/sck5 nmi x1a v ss x0a md2 md1 md0 x0 v cc x1 init v ss v cc pc0/dreq2 pc1/dack2 p c2/dstp2/deop2 pb0/dreq0 pb1/dack0 pb2/dstp0/deop0 pb3/dreq1 pb4/dack1 pb5/dstp1/deop1 pb6/iowr pb7/iord pa0/cs0 pa1/cs1 pa2/cs2 pa3/cs3 v ss v cc p80/in0/rdy p81/in1/bgrnt p82/in2/brq p83/rd p84/wr0 p85/in3/wr1 p90/sysclk p91 p92/mclk p93 p94/as v ss v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 p 20/d16 p 21/d17 p 22/d18 p 23/d19 p 24/d20 p 25/d21 p 26/d22 p 27/d23 p 30/d24 p 31/d25 p 32/d26 p 33/d27 p 34/d28 p 35/d29 p 36/d30 p 37/d31 v ss v cc p40/a00 p41/a01 p42/a02 p43/a03 p44/a04 p45/a05 p46/a06 p47/a07 p50/a08 p51/a09 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss v cc p60/a16 p61/a17 p62/a18 p63/a19 p64/a20 p65/a21 p66/a22 p67/a23 pg4/so5 pg3/si5 pg2/sck4 pg1/so4 pg0/si4 ph5/sck3 ph4/so3 ph3/si3 ph2/sck2 ph1/so2 ph0/si2 pi5/sck1 pi4/so1 pi3/si1 pi2/sck0 pi1/so0 pi0/si0 v cc v ss pj7/int15 pj6/int14 pj5/int13 pj4/int12 pj3/int11 pj2/int10 pj1/int9 pj0/int8 pk7/int7/atg pk6/int6/frck pk5/int5 pk4/int4 pk3/int3 pk2/int2 pk1/int1 pk0/int0 v cc v ss pl1/scl pl0/sda vss pm5/sck7/zin1/trg 5 pm4/so7/bin1/trg4 pm3/si7/ain1/trg3 pm2/sck6/zin0/trg 2 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pm1/so6/bin0/trg 1 pm0/si6/ain0/trg0 pn5/ppg5 pn4/ppg4 pn3/ppg3 pn2/ppg2 pn1/ppg1 pn0/ppg0 v cc v ss po7/oc7 po6/oc6 po5/oc5 po4/oc4 po3/oc3 po2/oc2 po1/oc1 po0/oc0 pp3/tot3 pp2/tot2 pp1/tot1 pp0/tot0 v cc v ss av ss /avrl avrh av cc an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 da2 da1 da0 da vc da vs 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
mb91350a series 5 pin description (continued) pin no. pin name circuit type description 1 to 8 d16 to d23 c external data bus bit 16 to bit 23. enabled in external bus mode. p20 to p27 available as a port in external bus 8-bit mode. 9 to 16 d24 to d31 c external data bus bit 24 to bit 31. enabled in external bus mode. p30 to p37 usable as port at single chip mode. 19 to 26 a00 to a07 c bits 0 to 7 of external address bu s. enabled in external bus mode. p40 to p47 usable as port at single chip mode. 27 to 34 a08 to a15 c bits 8 to 15 of external address bus. enabled in external bus mode. p50 to p57 usable as port at single chip mode. 37 to 41 a16 to a20 c bits 16 to 20 of external addres s bus. enabled in external bus mode. p60 to p64 available as a port either in single chip mode or with no external address bus in use. 42 to 44 a21 to a23 c bits 21 to 23 of external addres s bus. enabled in external bus mode. p65 to p67 available as a port either in single chip mode or with no external address bus in use. 47 to 48 da0, da1 ? d/a converter output pin. 49 da2 ? d/a converter output pin. 50 to 57 an0 to an7 g analog input pin. 58 to 61 an8 to an11 g analog input pin. 67 to 70 tot0 to tot3 d reload timer output port. this function is enabled when timer output is enabled. pp0 to pp3 general purpose input/output port. this function is enabled when the timer out- put function is disabled. 71 oc0 d output compare pin. po0 general purpose i/o. this function is av ailable as a port when the output com- pare output is not in use. 72 oc1 d output compare pin. po1 general purpose i/o. this function is av ailable as a port when the output com- pare output is not in use. 73 oc2 d output compare pin. po2 general purpose i/o. this function is av ailable as a port when the output com- pare output is not in use. 74 to 78 oc3 to oc7 d output compare pin. po3 to po7 general purpose i/o. this function is av ailable as a port when the output com- pare output is not in use. 81 ppg0 d ppg timer output pin. pn0 general purpose i/o. this function is av ailable as a port when the ppg timer out- put is not in use.
mb91350a series 6 (continued) pin no. pin name circuit type description 82 ppg1 d ppg timer output pin. pn1 general purpose i/o. this function is av ailable as a port when the ppg timer out- put is not in use. 83 ppg2 d ppg timer output pin. pn2 general purpose i/o. this function is av ailable as a port when the ppg timer out- put is not in use. 84 ppg3 d ppg timer output pin. pn3 general purpose i/o. this function is av ailable as a port when the ppg timer out- put is not in use. 85 ppg4 d ppg timer output pin. pn4 general purpose i/o. this function is av ailable as a port when the ppg timer out- put is not in use. 86 ppg5 d ppg timer output pin. pn5 general purpose i/o. this function is av ailable as a port when the ppg timer out- put is not in use. 87 si6 d data input for serial i/o6. since this input is used as required when serial i/o 6 is in input operation, the port output must remain off unless intentionally turned on. ain0 8/16-bit up/down counter input. since this input is used as required when en- abled, the port output must remain off unless intentionally turned on. trg0 external trigger input for ppg timer0. sinc e this input is used as required when enabled, the port output must remain off unless intentionally turned on. pm0 general purpose i/o. this function is ava ilable a port when the serial i/o, 8/16- bit up/down counter, and ppg timer outputs are not in use. 88 so6 d data output for serial i/o 6. this function is enabled when the serial i/o6 data out- put is enabled. bin0 8/16-bit up/down counter input. since this input is used as required when en- abled, the port output must remain off unless intentionally turned on. trg1 external trigger input for ppg timer1. sinc e this input is used as required when enabled, the port output must remain off unless intentionally turned on. pm1 general purpose i/o. this function is ava ilable a port when the serial i/o, 8/16- bit up/down counter, and ppg timer outputs are not in use. 89 sck6 d clock input/output for serial i/o 6. this fu nction is enabled when serial i/o6 is us- ing the external shift clock mode, or seri al i/o5 clock output function is enabled. zin0 8/16-bit up/down counter input. since this input is used as required when en- abled, the port output must remain off unless intentionally turned on. trg2 external trigger input for ppg timer2. sinc e this input is used as required when enabled, the port output must remain off unless intentionally turned on. pm2 general purpose i/o. this function is ava ilable a port when the serial i/o, 8/16- bit up/down counter, and ppg timer outputs are not in use.
mb91350a series 7 (continued) pin no. pin name circuit type description 90 si7 d data input for serial i/o 7. since this in put is used as required when serial i/o 7 is in input operation, the port output mu st remain off unless intentionally turned on. ain1 8/16-bit up/down counter input. since this input is used as required when en- abled, the port output must remain off unless intentionally turned on. trg3 external trigger input for ppg timer 3. since this input is used as required when enabled, the port output must remain off unless intentionally turned on. pm3 general purpose i/o. this function is ava ilable a port when the serial i/o, 8/16- bit up/down counter, and ppg ti mer outputs are not in use. 91 so7 d data output for serial i/o 7. this f unction is enabled when the serial i/o 7 data output is enabled. bin1 8/16-bit up/down counter input. since this input is used as required when en- abled, the port output must remain off unless intentionally turned on. trg4 external trigger input for ppg timer 4. since this input is used as required when enabled, the port output must remain off unless intentionally turned on. pm4 general purpose i/o. this function is ava ilable a port when the serial i/o, 8/16- bit up/down counter, and ppg ti mer outputs are not in use. 92 sck7 d clock input/output for serial i/o5. this func tion is enabled when serial i/o 7 is us- ing the external shift clock mode, or seri al i/o 5 clock output function is enabled. zin1 8/16-bit up/down counter input. since this input is used as required when en- abled, the port output must remain off unless intentionally turned on. trg5 external trigger input for ppg timer 5. since this input is used as required when enabled, the port output must remain off unless intentionally turned on. pm5 general purpose i/o. this function is ava ilable a port when the serial i/o, 8/16- bit up/down counter, and ppg ti mer outputs are not in use. 94 sda f clock input/output pin for i 2 c bus. this function is enabled when the i 2 c system is enabled for operation in standard mode . the port output must remain off unless intentionally turned on. (open drain input) pl0 general purpose input/output port. this fu nction is available as a port when the i 2 c system is disabled for o peration. (open drain input) 95 scl f clock input/output pin for i 2 c bus. this function is enabled when the i 2 c system is enabled for operation in standard mode . the port output must remain off unless intentionally turned on. (open drain input) pl1 general purpose input/output port. this fu nction is available as a port when the i 2 c system is disabled for o peration. (open drain input) 98 to 103 int0 to int5 e external interrupt input. since this input is used as required when the correspond- ing external interrupt is e nabled, the port output must remain off unless intention- ally turned on. pk0 to pk5 general purpose input/output port.
mb91350a series 8 (continued) pin no. pin name circuit type description 104 int6 e external interrupt input. since this input is used as required when the correspond- ing external interrupt is enabled, the port output must remain off unless intention- ally turned on. frck external clock input pin for freerun time r. since this input is used as required when selected as the external clock input for the free running timer, the port out- put must remain off unless intentionally turned on. pk6 general purpose input/output port. 105 int7 e external interrupt input. since this input is used as required when the correspond- ing external interrupt is enabled, the port output must remain off unless intention- ally turned on. atg external trigger input for a/d converter. si nce this input is used as required when selected as an a/d activation source, the port output must remain off unless in- tentionally turned on. pk7 general purpose input/output port. 106 to 113 int8 to int15 e external interrupt input. since this input is used as required when the correspond- ing external interrupt is enabled, the port output must remain off unless intention- ally turned on. pj0 to pj7 general purpose input/output port. 116 si0 d uart0 data input. since this input is us ed as required when uart0 is in input operation, the port output must remain off unless intentionally turned on. pi0 general purpose input/output port. 117 so0 d uart0 data output. this function is enabled when the uart0 data output is en- abled. pi1 general purpose input/output port. this function is enabled when the data output function of uart0 is disabled. 118 sck0 d uart0 clock input/output pin. this func tion is enabled either when clock output enabled or when uart0 inputs t he external clock signal. pi2 general purpose input/output port. this f unction is enabled when uart0 is not using the external clock signal with the uart0 clock output function disabled. 119 si1 d uart1 data input. since this input is us ed as required when uart1 is in input operation, the port output must remain off unless intentionally turned on. pi3 general purpose input/output port. 120 so1 d uart1 data outpu. this function is enabl ed when the uart1 data output is en- abled. pi4 general purpose input/output port. this function is enabled when the data output function of uart1 is disabled. 121 sck1 d uart1 clock input/output pin. this func tion is enabled either when clock output enabled or when uart1 inputs t he external clock signal. pi5 general purpose input/output port. this f unction is enabled when uart1 is not using the external clock signal with the uart1 clock output function disabled.
mb91350a series 9 (continued) pin no. pin name circuit type description 122 si2 d uart2 data input. since this input is used as required when uart2 is in input operation, the port output must remain off unless intentionally turned on. ph0 general purpose input/output port. 123 so2 d uart2 data outpu. this function is enabled when the uart2 data output is en- abled. ph1 general purpose input/output port. this function is enabled when the data output function of uart2 is disabled. 124 sck2 d uart2 clock input/output pin. this func tion is enabled either when the uart2 clock output is enabled or when ua rt2 inputs the external clock signal. ph2 general purpose input/output port. this function is enabled when uart2 is not using the external clock signal with t he uart2 clock output function disabled. 125 si3 d uart3 data input. since this input is used as required when uart3 is in input operation, the port output must remain off unless intentionally turned on. ph3 general purpose input/output port. 126 so3 d uart3 data outpu. this function is enabled when the uart3 data output is en- abled. ph4 general purpose input/output port. this function is enabled when the data output function of uart3 is disabled. 127 sck3 d uart0 clock input/output pin. this func tion is enabled either when the uart3 clock output is enabled or when ua rt3 inputs the external clock signal. ph5 general purpose input/output port. this function is enabled when uart3 is not using the external clock signal with t he uart3 clock output function disabled. 128 si4 d uart4 data input. since this input is used as required when uart4 is in input operation, the port output must remain off unless intentionally turned on. pg0 general purpose input/output port. 129 so4 d uart4 data output. this function is enabled when the uart4 data output is en- abled. pg1 general purpose input/output port. this function is enabled when the data output function of uart4 is disabled. 130 sck4 d uart4 clock input/output pin. this func tion is enabled either when the uart4 clock output is enabled or when ua rt4 inputs the external clock signal. pg2 general purpose input/output port. this function is enabled when uart4 is not using the external clock signal with t he uart4 clock output function disabled. 131 si5 d data input for serial i/o5. since this input is used as required when serial i/o5 is in input operation, the port output must remain off unless intentionally turned on. pg3 general purpose input/output port. 132 so5 d data output for serial i/o5. this function is enabled when the serial i/o5 data out- put is enabled. pg4 general purpose input/output port. this function is enabled when the i/o5 data output function is disabled.
mb91350a series 10 (continued) pin no. pin name circuit type description 133 sck5 d clock innput/output for serial i/o5. this function is enabled when serial i/o5 is using the external shift clock mode, or serial i/o5 clock output function is en- abled. pg5 general purpose input/output port. this fu nction is enabled when serial i/o5 is not using the external shift clock mode with the serial i/o5 clock output function disabled. 134 nmi h nmi (non maskable interrupt) input 135 x1a b output clock cycle time. sub clock 137 x0a b input clock cycle time. sub clock 138 to 140 md2 to md0 h, j 2 to 0mode pins. the levels applied to th ese pins set the basic operating mode. connect vcc or vss. input circuit configuration: the production model (masked-rom model) is type ?h?. the flash rom model is type ?j?. 141 x0 a input clock cycle time. main clock 143 x1 a output clock cycle time. main clock 144 init i external reset input 147 dreq2 c external input for dma transfer requests. since this input is used as required when selected as a dma start source, t he port output must remain off unless in- tentionally turned on. pc0 general purpose input/output port. 148 dack2 c external acknowledge output for dma transf er requests. this function is enabled when the transfer request accept ance output for dma is enabled. pc1 general purpose input/output port. this fu nction is enabled w hen the transfer re- quest acceptance output for dma is enabled. 149 deop2 c completion output for dma external transfe r. this function is enabled when the external transfer end output for dma is enabled. dstp2 stop input for dma external transfer. th is function is enabled when the external transfer stop input for dma is enabled. pc2 general purpose input/output port. this function is enabled when the external transfer end output and external transf er stop input for dma are disabled. 150 dreq0 c external input for dma transfer requests. since this input is used as required when selected as a dma start source, t he port output must remain off unless in- tentionally turned on. pb0 general purpose input/output port. 151 dack0 c external acknowledge output for dma transf er requests. this function is enabled when the transfer request accept ance output for dma is enabled. pb1 general purpose input/output port. this fu nction is enabled w hen the transfer re- quest acceptance output for dma is disabled.
mb91350a series 11 (continued) pin no. pin name circuit type description 152 deop0 c completion output for dma external trans fer. this function is enabled when the external transfer end out put for dma is enabled. dstp0 stop input for dma external transfer. this function is enabled when the external transfer stop input for dma is enabled. pb2 general purpose input/output port. this fu nction is enabled when the external transfer end output and external tr ansfer stop input for dma are disabled. 153 dreq1 c external input for dma transfer requests. since this input is used as required when selected as a dma start source, the port output must remain off unless in- tentionally turned on. pb3 general purpose input/output port. 154 dack1 c external acknowledge output for dma transfe r requests. this function is enabled when the transfer request accept ance output for dma is enabled. pb4 general purpose input/output port. this fu nction is enabled when the external transfer request acceptance output for dma is disabled. 155 deop1 c completion output for dma external trans fer. this function is enabled when the external transfer end out put for dma is enabled. dstp1 stop input for dma external transfer. this function is enabled when the external transfer stop input for dma is enabled. pb5 general purpose input/output port. this fu nction is enabled when the external transfer end output and external tr ansfer stop input for dma are disabled. 156 iowr c write strobe output for dma fly-by tr ansfer. this function is enabled when the dma fly-by transfer write strobe output is enabled. pb6 general purpose input/output port. this f unction is enabled when the dma fly-by transfer write strobe output is disabled. 157 iord c read storobe output for dma fly-by transfe r. this function is enabled when the dma fly-by transfer read strobe output is enabled. pb7 general purpose input/output port. this f unction is enabled when the dma fly-by transfer read strobe output is disabled. 158 cs0 c chip select 0 output. enable at external bus mode pa0 general purpose input/output port. this is enabled at single chip mode. 159 cs1 c chip select 1 output. this function is e nabled when the chip select 1 output is en- abled. pa1 general purpose input/output port. this function is enabled when the chip select 1 output is disabled. 160 cs2 c chip select 2 output. this function is e nabled when the chip select 2 output is en- abled. pa2 general purpose input/output port. this function is enabled when the chip select 2 output is disabled.
mb91350a series 12 (continued) pin no. pin name circuit type description 161 cs3 c chip select 3 output. this function is enab led when the chip select 3 output is en- abled. pa3 general purpose input/output port. this f unction is enabled when the chip select 3 output is disabled. 164 rdy d external ready input. the pi n has this function when external ready input is en- abled. in0 input capture input pin. since this input is used as required when selected as an input capture input, the port output must remain off unless intentionally turned on. p80 general purpose input/output port. this function is enabled when external ready signal input is disabled. 165 bgrnt d acknowledge output for external bus rele ase. outputs ?l? when the external bus is released. the pin has this function when output is enabled. in1 input capture input pin. since this input is used as required when selected as an input capture input, the port output must remain off unless intentionally turned on. p81 general purpose input/output port. this func tion is enabled when external bus re- lease acknowledge output is disabled. 166 brq d external bus release request input. input ?1? to request release of the external bus. the pin has this function when input is enabled. in2 input capture input pin. since this input is used as required when selected as an input capture input, the port output must remain off unless intentionally turned on. p82 general purpose input/output port. the pi n has this function when the external bus release request input is disabled. 167 rd d external bus read strobe output. it is available in the external bus mode. p83 general purpose input/output port. this is enabled at single chip mode. 168 wr0 d external bus write strobe output. it is available in the external bus mode. p84 general purpose input/output port. this is enabled at single chip mode. 169 wr1 d external bus write strobe output. this function is enabled when wr1 output is en- abled in external bus mode. in3 input capture input pin. since this input is used as required when selected as an input capture input, the port output must remain off unless intentionally turned on. p85 general purpose input/output port. the pi n has this function when the external bus write-enable output is disabled. 170 sysclk c system clock output the pin has this f unction when system clock output is en- abled. this outputs the same clock as th e external bus operating frequency. (out- put halts in stop mode.) p90 general purpose input/output port. the pin has this function when system clock output is disabled. 171 p91 c general purpose input/output port.
mb91350a series 13 (continued) ? power supply and gnd pins pin no. pin name circuit type description 172 mclk c memory clock output. this function is enabled when the memory clock output is enabled. this outputs the same clock as the external bus operating frequency. (output halts in sleep/stop mode.) p92 general purpose input/output port. this function is enabled when the memory clock output is disabled. 173 p93 c general purpose input/output port. 174 as c address strobe output. this function is enabled when address strobe output is enabled. p94 general purpose input/output port. this fu nction is enabled when address load output is disabled. pin no. pin name description 17, 35, 65, 79, 93, 96, 114, 136, 145, 162, 175 v ss gnd pins. apply equal potential to all of the pins. 18, 36, 66, 80, 97, 115, 142, 146, 163, 176 v cc 3.3 v power supply pin. apply equal potential to all of the pins. 45 da vs gnd pin for d/a converter 46 da vc power supply pin for d/a converter 62 av cc analog power supply pin for a/d converter 63 avrh reference power supply pin for a/d converter 64 av ss /avrl analog gnd pin for a/d converter
mb91350a series 14 i/o circuit type (continued) type circuit type remarks a oscillation feedback resistance: approx. 1 m ? b oscillation feedback resistance for low speed (subclock oscillation): approx. 7 m ? c cmos level output cmos level input with standby control with pull-up control pull-up resistance = approx. 50 k ? (typ) i ol = 8 ma d cmos level output cmos level hysteresis input with standby control with pull-up control pull-up resistance = approx. 50 k ? (typ) i ol = 4 ma x1 standby control x0 clock input x 1a standby control x 0a clock input standby control digital input digital output digital output pull-up control standby control digital input digital output digital output pull-up control
mb91350a series 15 (continued) type circuit type remarks e cmos level output cmos level hysteresis input with stand voltage of 5 v i ol = 4 ma f nch open drain output cmos level hysteresis input with standby control with stand voltage of 5 v i ol = 15 ma g analog input with switch h cmos level hysteresis input i cmos level hysteresis input with pull-up resistor pull-up resistance = approx. 50 k ? (typ) digital input digital output digital output standby control digital input digital output control analog input digital input digital input
mb91350a series 16 (continued) type circuit type remarks j cmos level input flash product only diffused resistor mode input control signal
mb91350a series 17 handling devices ? preventing latchup latch-up may occur in a cmos ic if a voltage greater than vcc or less than vss is applied to an input or output pin or if an above-rating voltage is applied between vcc and vss. a latchup,if it occurs, significantly increases the power supply current and may cause thermal destructi on of an element. when you use a cmos ic, be very careful not to exceed the maximum rating. treatment of unused input pins do not leave an unused input pin open, since it may caus e a malfunction. handle by, for example, using a pull- up or pull-down resistor. about power supply pins in products with multiple v cc or v ss pins, the pins of the same potentia l are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to an external power supply and a ground line to lower the electro- magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cerami c bypass capacitor of approximately 0.1 f between v cc and v ss near this device. about crystal oscillator circuit noise near the x0, x1, x0a and x1a pins may cause the device to malfunction. design the circuit board so that x0, x1, x0a, x1a, the crystal oscillator (or ceramic osc illator), and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended to design the pc board ar twork with the x0, x1, x0 a and x1a pins surrounded by ground plane because stable operation can be expected with such a layout. notes on using external clock when external clock is selected, supply it to x0 pi n generally, and simultaneously the opposite phase clock to x0 must be supplied to x1 pin. however, in this case the stop mode(oscillator stop mode) must not be used. (this is because the x1 pin stops at high level output in stop mode.) using an external clock (normal) clock control block take the oscillation stabilization wait time during low level input to the init pin. x0 x1 note: stop mode (oscillation stop mode) cannot be used.
mb91350a series 18 notes on not using the sub clock when no oscillator is connected to the x0a and x1a pins, pull down the x0a pin and open the x1a pin. treatment of nc and open pins pins marked as nc and open must be left open-circuit. mode pins (md0 to md2) these pins should be connected directly to v cc or v ss . to prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and v cc or v ss is as short as possible and the connection impedance is low. operation at start-up the init pin must be at low level when the power supply is turned on. immediately after the power supply is turn ed on, hold the low level input to the init pin for the settling time required for the oscillator circuit to take the oscillation st abilization wait time for the oscillator circuit. (for init via the init pin, the oscillation stabilization wait time se tting is initialized to the minimum value.) about oscillation input at power on when turning the power on, maintain clock input until the device is released from the oscillation stabilization wait state. caution on operations during pll clock mode even if the oscillator comes off or the clock input stops wi th the pll clock selected for this microcontroller, the microcontroller may continue to operate at the free-runni ng frequency of the pll?s internal self-oscillating oscil- lator circuit. performance of this operation, however, cannot be guaranteed. external bus setting this model guarantees an external bus frequency of 25 mhz. setting the base clock frequency to 50 mhz with divr1 (external bus base clock division setting register) initialized sets the external bus frequency also to 50 mhz. before changing the base clock frequency, set the external bus frequency not exceeding 25 mhz. mclk and sysclk mclk and sysclk has a difference that mclk stops in sleep/stop mode but sysclk stops only in stop mode. use either depending on each application. upon initialization, mclk becomes invalid (port) and sysclk becomes valid. to use mclk, set the port function register (pfr) to select the use of that clock. pull-up control connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the ? electrical characteristics 4. ac characteristics (4) normal bu s access read/write operation, (5) multiplex bus access read/write operati on and (7) hold timing?. even the port for which a pull-up resistor has been set is invalid in stop mode with hiz = 1 or in hardware standby mode. x0 x1 mb91350a open
mb91350a series 19 sub clock select immediately after switching from main clock mode to subclock mode for the clock source, insert at least one nop instruction. bit search module the bsd0, bsd1, and bdsc register s are accessed only in words. d-bus memory do not allocate the code area in memory on the d-bus because no instruction fetch takes place to the d-bus. executing an instruction fetch to the d-bus area causes wrong data to be interpreted as code, possibly letting the device to run out of control. low power consumption mode to enter the sleep or stop mode, be sure to read the standby control register (s tcr) immediately after writing to it. precisely, use the following sequence. set the i flag, ilm, and icr to, after returning from standby mode, branch to the interrupt handler having caused the device to return. switch shared port function to switch between the use as a port an d the use as a dedicated pin, use the port function register (pfr). note, however, that bus pins are switched depending on external bus settings. pre-fetch when accessing a prefetch-enabled little endian area, be su re to use word access (in 32-bit, word length) only. byte or halfword access results in wrong data read. i/o port access ports are accessed only in bytes. built-in ram immediately after a reset is canceled, the internal ram a llocation restricting function is still working, allowing only 4 kb to be used for data and for program execution irrespective of the on-chip ram capacity. (ldi #0x0b, r0) (ldi #_clkr, r12) stb r0, @r12 // sub-clock mode nop // must insert nop instruction (ldi #value_of_standby, r0) (ldi #_stcr, r12) stb r0, @r12 // set stop/sleep bit ldub @r12, r0 // must read stcr ldub @r12, r0 // after reading, go into standby mode nop // must insert nop *5 nop nop nop nop
mb91350a series 20 flash memory in programming mode, flash memory cannot be used as an interrupt vector table. a reset is possible. notes on the ps register as the ps register is processed by some instructio ns in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the ps register to be updated. as the microcontroller is designed to carry out reproces sing correctly upon returning from such an eit event, it performs operations before and after t he eit as specified in either case. 1. the following operations are performed when the instru ction followed by a divou/divos instruction results in: (a) acceptance of a user interrupt or nmi, (b) single-stepping, or (c) a br eak at a data event or emulator menu. ? the d0 and d1 flags are updated in advance. ? an eit handling routine (user interr upt, nmi, or emulator) is executed. ? upon returning from the eit, the divou/divos inst ruction is executed and the d0 and d1 flags are updated to the same values as in (1). 2. the following operations are per formed when the orccr/stilm/movri and ps instructions are executed. ? the ps register is updated in advance. ? an eit handling routine (user interr upt, nmi, or emulator) is executed. ? upon returning from the eit, the above instructions are executed and the ps register is updated to the same value as in (1).
mb91350a series 21 [note on debugger] ? step execution of reti command if an interrupt occurs frequently duri ng single-stepping, the corresponding in terrupt handling routine is executed repeatedly. this will prevent the main routine and low-in terrupt-level programs from being executed. (whenever reti is single-stepped when interrupts by the timebase timer have been enabled, for example, the timebase timer routine causes a break at the beginning.) disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debug- ging. break function if the address at which to cause a hardware break (i ncluding a event break) is set to the address currently contained in the system stack pointer or in the area containing the stack pointer, the user program causes a break after execution of one instruction. to prevent this, do not set (word) access to the area co ntaining the address in the system stack pointer as the target of a hardware break (including an event break). internal rom area do not set an area of internal rom as a dmac transfer destination. simultaneous occurrences of a software break (inte instruction) and a user interrupt/nmi when an inte instruction and a user interrupt/nmi ar e accepted simultaneously, the emulator debugger reacts as follows. the emulator debugger stops while indi cating a location in the user program, which is not a user-specified breakpoint. (it stops with the beginning of the user interrupt/nmi handling routine indicated.) the user program cannot be re-executed correctly. to prevent this problem, follow the instructions below. when a software break and a user interrupt/nmi occu r simultaneously, the emulator debugger may react as follows. the debugger stops pointing to a loca tion other than the programmed breakpoints. the halted program is not re-executed correctly. if this symptom occurs, use a hardware break in plac e of a hardware break. when using a monitor debugger, do not set a break at the relevant location. a stack pointer placed in an area set for a dsu oper and break can cause a malfunction. do not apply a data event break to access to the area containing the address of a system stack pointer.
mb91350a series 22 block diagram dmac 5 channels port i/f 1 channel i 2 c fr cpu bus converter 32 32 32 32 32 ? / / / / bit search ram 16 kb (stack) clock control interrupt dmac (dma controller) 16 channels external interrupt 3 channels d/a 8 channels output compare 4 channels input capture 16-bit free-run timer 2 channels 8/16-bit up/down counter 4 channels reload timer 6 channels ppg external memory i/f clock timer
mb91350a series 23 cpu and control unit internal architecture the fr family cpu is a high performance core bas ed on a risc architecture while incorporating advanced instructions for embedded controller applications. 1. features risc architecture employed. basic instruct ions: executed at 1 instruction per cycle general-purpose registers: 32-bit 16 registers 4gb linear memory space multiplier integrated. 32-bit x 32-bit multiplication: 5 cycles. 16-bit x 16-bit multiplication: 3 cycles enhanced interrupt servicing. fast response speed (6 cycles). multiple interrupts supported. level masking (16 levels) enhanced i/o manipulation instructions. memory-to-memory transfer instructions, bit manipulation instructions high code efficiency. basic instruction word length: 16-bit low-power consumption. sleep mode and stop mode gear function
mb91350a series 24 2. internal architecture the fr-family cpu has a harvard architecture in which the instruction and data buses are separated. the 32-bit/16-bit bus converter is connected to a 32-bi t bus (f-bus), providing an interface between the cpu and peripheral resources. the harvard-princeton bus converter is connected to both of the i-bus and d-bus, providing an interface between the cpu and the bus controller. fr cpu data ram 32-bit 16-bit bus converter harvard princeton bus converter d-bus i-bus d address i address external addres s external data d data address data 16 16 24 32 32 32 32 32 32 i data r-bus f-bus p eripherals resource internal i/o bus controller
mb91350a series 25 3. programming model basic programming model r0 r1 r12 r13 r14 r15 pc ps ? ilm ? scr ccr tbr rp ssp usp mdh mdl ac fp sp xxxx xxxx h xxxx xxxx h 0000 0000 h 32-bit initial value: general purpose registers program counter program status table base register return pointer system stack pointer user stack pointer multiplication and division result register
mb91350a series 26 4. register general purpose registers registers r0 to r15 are general-purpose registers. th e registers are used as the accumulator and memory access pointers for cpu operations. of these 16 registers, the registers listed below are int ended for special applications, for which some instructions are enhanced. r13 : virtual accumulator r14 : frame pointer r15 : stack pointer the initial values of r0 to r14 after a reset are indeterminate. r15 is initialized to 0000 0000 h (ssp value). ps (program status) this register holds the program status and is divided into the ilm, scr, and ccr. the undefined bits in the following illustration are all reserv ed bits. reading these bits always returns ?0?. writing to them has no effect. r 0 r 1 r 12 r 13 r 14 r 15 ac fp sp xxxx xxxx h xxxx xxxx h 0000 0000 h 32-bit initial value: bit position ps 31 20 16 ilm scr ccr 10 7 8 0 ? ?
mb91350a series 27 ccr (condition code register ) scr (system condition code register ) flag for step dividing stores intermediate data for stepwise multiplication operations. step trace trap flag a flag specifying whether the step trac e trap function is enabled or not. emulator use step trace trap function. the functi on cannot be used by the user program when using the emulator. ilm this register stores the interrupt level mask value. t he value in the ilm register is used as the level mask. initialized to ?15? (01111 b ) by a reset. pc (program counter) the program counter contains the address of the instruction currently being executed. the initial value after a reset is indeterminate. s : stack flag. cleared to ?0? by a reset. i : interrupt enable flag. cleared to ?0? by a reset. n : negative flag. the initial val ue after a reset is indeterminate. z : zero flag. the initial value after a reset is indeterminate. v : overflow flag. the initial valu e after a reset is indeterminate. c : carry flag. the initial value after a reset is indeterminate. initial value: - - 00xxxx b ccr 76543210 ?? sinzvc initial value: xx0 b scr 10 9 8 d1 d0 t initial value: 01111 b ilm 20 19 18 17 16 ilm4 ilm3 ilm2 ilm1 ilm 0 initial value: xxxxxxxx h pc 31 0 p c
mb91350a series 28 tbr (table base register) the table base register contains the start address of the vector table used for servicing eit events. the initial value after a reset is 000ffc00 h rp (return pointer) the return pointer contains the address to which to return from a subroutine. when the call instruction is executed, the value in the pc is transferred to the rp. when the ret instruction is executed, the va lue in the rp is transferred to the pc. the initial value after a reset is indeterminate. ssp (system stack pointer) the ssp is the system stack pointer and functions as r15 when the s flag is ?0?. the ssp can be explicitly specified. the ssp is also used as the stack pointer that specifies the stack for saving the ps and pc when an eit event occurs. the initial value after a reset is 00000000 h usp (user stack pointer) the usp is the user stack pointer and functions as r15 when the s flag is ?1?. the ssp can be explicitly specified. the initial value after a reset is indeterminate. this pointer cannot be used by the reti instruction. initial value: 000ffc00 h tbr 31 0 t br initial value: xxxxxxxx h rp 31 0 r p initial value: 00000000 h ssp 31 0 s sp initial value: xxxxxxxx h usp 31 0 u sp
mb91350a series 29 multiply & divide registers these registers hold the results of a multiplication or division. ea ch of them is 32-bit long. the initial value after a reset is indeterminate. multiplication and division result register 31 0 m dh m dl
mb91350a series 30 mode settings the fr family uses mode pins (md2 to md0) and a mode register (modr) to set the operation mode. 1. mode pins the md2, md1, and md0 pins specify ho w the mode vector fetch is performed. values other than those listed in the table are prohibited. 2. mode register (modr) the data written to the mode register at 000f fff8 h using mode vector fetch is called mode data. after an operation mode has been set in the mode regist er (modr), the device operates in the operation mode. the mode register is set by any reset source. user programs cannot write data to the mode register. note : conventionally the fr family has nothing at addresses (0000 07ff h ) in the mode register. [bit 7 to bit 3] reserved bit be sure to set this bit to ?00000?. operation is not guaranteed when any value other than ?00000? is set. [bit 2] roma (internal rom enable bit) the roma bit is used to set whether to enable the internal f-bus ram and f-bus rom areas. mode pins mode name reset vector access area remarks md2 md1 md0 0 0 0 internal rom mode vector internal 0 0 1 external rom mode vector external the bus wi dth is specified by the mode register. roma function remarks 0 external rom mode internal f-bus ram is valid; the area (80000 h to 100000 h ) of internal rom is used as an external area. 1 internal rom mode internal f-bus ram and f-bus rom become valid. modr initial value 000f fff8 h xxxxxxxx b 76543210 0 0 0 0 0 roma wth1 wth0 operation mode setting bits
mb91350a series 31 [bit 1, bit 0] wth1, wth0 (bus width setting bits) used to set the bus width to be used in external bus mode. when the operation mode is the external bus mode, this value is set in bits bw1 and bw0 in amd0 (cs0 area). wth1 wth0 function remarks 0 0 8-bit bus width external bus mode 0 1 16-bit bus width 10 ? setting disabled 1 1 single chip mode single chip mode
mb91350a series 32 memory space 1. memory space the fr family has 4 gb of logical address space (2 32 addresses) available to the cpu by linear access. direct addressing areas the following address space areas are used as i/o areas. these areas are called direct addressing areas, in wh ich the address of an operand can be specified directly during an instruction. the size of directly addressable areas depends on the length of the data being accessed as shown below. byte data access : 000 h to 0ff h half word data access : 000 h to 1ff h word data access : 000 h to 3ff h 2. memory map memory map of MB91F355A/mb91355a each mode is set depending on t he mode vector fetch after init is negated. the mb91v350a uses the area of 512 kb of internal rom as emulation ram in the mb91355a memory map. the internal ram (instruction) has been expanded from 8 kb to 16 kb. the available area of internal ram is restricted immedi ately after a reset is canceled. when the setting of the available area is updated, the instruction must be followed by at least 1 nop instruction. 0 008 0000 h 0 000 0000 h 0 000 0400 h 0 001 0000 h 0 003 e000 h 0 004 0000 h 0 004 4000 h 0 005 0000 h 0 010 0000 h f fff ffff h i/o i/o i/o i/o i/o i/o single chip mode internal rom external bus mode access disallowed direct addressing area refer to 3. i/o map built-in ram8 kb (executable) built-in ram 512 kb access disallowed access disallowed built-in ram8 kb ( executable ) built-in ram 512 kb external area access disallowed built-in ram 8 kb (executable) external area built-in ram 16 kb (stack) access disallowed external rom external bus mode external area access disallowed access disallowed built-in ram16 kb (stack) built-in ram16 kb (stack)
mb91350a series 33 memory map of mb91354a each mode is set depending on t he mode vector fetch after init is negated. the available area of internal ram is restricted immedi ately after a reset is canceled. when the setting of the available area is updated, the instruction must be followed by at least 1 nop instruction. 0 00a 0000 h 0 000 0000 h 0 000 0400 h 0 001 0000 h 0 003 e000 h 0 004 0000 h 0 004 2000 h 0 005 0000 h 0 010 0000 h f fff ffff h i/o i/o i/o i/o i/o i/o single chip mode internal rom external bus mode access disallowed direct addressing area refer to 3. i/o map built-in ram 8 kb (executable) built-in rom 384 kb access disallowed access disallowed built-in ram 8 kb (executable) built-in rom 384 kb external area access disallowed built-in ram 8 kb (executable) external area built-in ram 8 kb (stack) access disallowed external rom external bus mode external area access disallowed access disallowed built-in ram 8 kb (stack) built-in ram 8 kb (stack)
mb91350a series 34 3. i/o map this shows the location of the various periph eral resource register s in the memory space. (how to read the table) note : initial values of register bits are represented as follows : (continued) ?1? : initial value is ?1?. ?0? : initial value: ?0?. ?x? : initial value is ?x?. ? ? ? : no physical register at this location address register block diagram + 0 + 1 + 2 + 3 000000 h ?? pdr2 [r/w] b xxxxxxxx pdr3 [r/w] b xxxxxxxx t-unit port data register 000004 h pdr4 [r/w] b xxxxxxxx pdr5 [r/w] b xxxxxxxx pdr6 [r/w] b xxxxxxxx ? 000008 h pdr8 [r/w] b - - xxxxxx pdr9 [r/w] b - - - xxxxx pdra [r/w] b - - - - xxxx pdrb [r/w] b xxxxxxxx 00000c h pdrc [r/w] b - - - - - xxx ? 000010 h pdrg[r/w] b - - xxxxxx pdrh [r/w] b - - xxxxxx pdri [r/w] b - - xxxxxx pdrj [r/w] b xxxxxxxx r-bus port data register 000014 h pdrk [r/w] b xxxxxxxx pdrl [r/w] b - - - - - - xx pdrm [r/w] b - - xxxxxx pdrn [r/w] b - - xxxxxx 000018 h pdro [r/w] b xxxxxxxx pdrp [r/w] b - - - - xxxx ?? 00001c h ? 000020 h ???? reserved 000024 h smcs5 [r/w] b, h* 3 00000010 - - - - 00 - - ses5 [r/w] b* 3 - - - - - - 00 sdr5 [r/w] b* 3 xxxxxxxx sio 5* 3 address register block diagram + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b xxxxxxxx pdr1 [r/w] b xxxxxxxx pdr2 [r/w] b xxxxxxxx pdr3 [r/w] b xxxxxxxx t-unit port data register read/write attribute, access unit (b : byte, h : half word, w : word) initial value after a reset register name (first-column register at address 4n, second-column register at address 4n + 2) location of left-most register (when usin g word access, the register in column 1 is in the msb side of the data.)
mb91350a series 35 (continued) address register block diagram + 0 + 1 + 2 + 3 000028 h smcs6 [r/w] b, h 00000010 - - - - 00 - - ses6 [r/w] b - - - - - - 00 sdr6 [r/w] b xxxxxxxx sio 6 00002c h smcs7 [r/w] b, h 00000010 - - - - 00 - - ses7 [r/w] b - - - - - - 00 sdr7 [r/w] b xxxxxxxx sio 7 000030 h ?? cdcr5 [r/w] b 0---1111 ? * 1 sio prescaler 5 000034 h cdcr6 [r/w] b 0 - - - 1111 ? * 1 cdcr7 [r/w] b 0 - - - 1111 ? * 1 sio prescaler 6, 7 000038 h ? srcl5 [w] b - - - - - - - - srcl6 [w] b - - - - - - - - srcl7 [w] b - - - - - - - - sio5 to sio7 00003c h ???? reserved 000040 h eirr0 [r/w] b, h, w 00000000 enir0 [r/w] b, h, w 00000000 elvr0 [r/w] b, h, w 00000000 ext int (int0 to int7) 000044 h dicr [r/w] b, h, w - - - - - - - 0 hrcl [r/w] b, h, w 0 - - 11111 ? dlyi/i-unit 000048 h tmrlr [w] h, w xxxxxxxx xxxxxxxx tmr [r] h, w xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr [r/w] b, h, w - - - - 0000 00000000 000050 h tmrlr [w] h, w xxxxxxxx xxxxxxxx tmr [r] h, w xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr [r/w] b, h, w - - - - 0000 00000000 000058 h tmrlr [w] h, w xxxxxxxx xxxxxxxx tmr [r] h, w xxxxxxxx xxxxxxxx reload timer 2 00005c h ? tmcsr [r/w] b, h, w - - - - 0000 00000000 000060 h ssr [r/w] b, h, w 00001000 sidr/sodr [r/w] b, h, w xxxxxxxx scr [r/w] b, h, w 00000100 smr [r/w] b, h, w 00 - - 0 - - - uart0 000064 h utim [r] h (utimr [w] h) 00000000 00000000 drcl [w] b - - - - - - - - utimc [r/w] b 0 - - 00001 u-timer/ uart 0 000068 h ssr [r/w] b, h, w 00001000 sidr/sodr [r/w] b, h, w xxxxxxxx scr [r/w] b, h, w 00000100 smr [r/w] b, h, w 00 - - 0 - - - uart1 00006c h utim [r] h (utimr [w] h) 00000000 00000000 drcl [w] b - - - - - - - - utimc [r/w] b 0 - - 00001 u-timer/ uart 1 000070 h ssr [r/w] b, h, w 00001000 sidr/sodr [r/w] b, h, w xxxxxxxx scr [r/w] b, h, w 00000100 smr [r/w] b, h, w 00 - - 0 - - - uart2 000074 h utim [r] h (utimr [w] h) 00000000 00000000 drcl [w] b - - - - - - - - utimc [r/w] b 0 - - 00001 u-timer/ uart 2
mb91350a series 36 (continued) address register block diagram + 0 + 1 + 2 + 3 000078 h adcs2 [r/w]b, h, w x000xx00 adcs1 [r/w]b, h, w 000x0000 adct [r/w] h, w xxxxxxxx_xxxxxxxx a/d converter: successive approxima- tion 00007c h adth0 [r] b, h, w xxxxxxxx adtl0 [r] b, h, w 000000xx adth1 [r] b, h, w xxxxxxxx adtl1 [r] b, h, w 000000xx 000080 h adth2 [r] b, h, w xxxxxxxx adtl2 [r] b, h, w 000000xx adth3 [r] b, h, w xxxxxxxx adtl3 [r] b, h, w 000000xx 000084 h ? dacr2 [r/w] b, h, w - - - - - - - 0 dacr1 [r/w] b, h, w - - - - - - - 0 dacr0 [r/w] b, h, w - - - - - - - 0 d/a converter 000088 h ? dadr2 [r/w] b, h, w xxxxxxxx dadr1 [r/w] b, h, w xxxxxxxx dadr0 [r/w] b, h, w xxxxxxxx 00008c h ???? reserved 000090 h ???? * 1 reserved 000094 h ibcr [r/w] b, h, w 00000000 ibsr [r] b, h, w 00000000 itba [r/w] b, h, w - - - - - - 00 00000000 i 2 c interface 000098 h itmk [r/w] b, h, w 00 - - - - 11 11111111 ismk [r/w] b, h, w 01111111 isba [r/w] b, h, w - 0000000 00009c h ? idar [r/w] b, h, w 00000000 iccr [r/w] b, h, w 0 - 011111 idbl [r/w] b, h, w - - - - - - - 0 0000a0 h ?? * 1 ?? * 1 reserved 0000a4 h ?? * 1 ? * 1 ? * 1 0000a8 h tmrlr [w] h, w xxxxxxxx xxxxxxxx tmr [r] h, w xxxxxxxx xxxxxxxx reload timer 3 0000ac h ? tmcsr [r/w] b, h, w - - - - 0000 00000000 0000b0 h rcr1 [w] b, h, w 00000000 rcr0 [w] b, h, w 00000000 udcr1 [r] b, h, w 00000000 udcr0 [r] b, h, w 00000000 8/16-bit up/down counter 0, 1 0000b4 h ccrh0 [r/w] b, h, w 00001000 ccrl0 [r/w] b, h, w 00001000 ? csr0 [r/w] b, h, w 00000000 0000b8 h ccrh1 [r/w] b, h, w 00001000 ccrl1 [r/w] b, h, w 00001000 ? csr1 [r/w] b, h, w 00000000 0000bc h ???? reserved 0000c0 h ssr [r/w] b, h, w 00001000 sidr/sodr [r/w] b, h, w xxxxxxxx scr [r/w] b, h, w 00000100 smr [r/w] b, h, w 00 - - 0 - - - uart3 0000c4 h utim [r] h (utimr [w] h) 00000000 00000000 ? utimc [r/w] b 0 - - 00001 u-timer/ uart 3 0000c8 h ssr [r/w] b, h, w 00001000 sidr/sodr [r/w] b, h, w xxxxxxxx scr [r/w] b, h, w 00000100 smr [r/w] b, h, w 00 - - 0 - - - uart4
mb91350a series 37 (continued) address register block diagram + 0 + 1 + 2 + 3 0000cc h utim [r] h (utimr [w] h) 00000000 00000000 ? utimc [r/w] b 0 - - 00001 u-timer/ uart 4 0000d0 h eirr1 [r/w] b, h, w 00000000 enir1 [r/w]b, h, w 00000000 elvr1 [r/w] b, h, w 00000000 ext int (int8-15) 0000d4 h tcdt [r/w] h, w 00000000 00000000 ? tccs [r/w] b, h, w 00000000 16-bit free run timer 0000d8 h ipcp1 [r] h, w xxxxxxxx xxxxxxxx ipcp0 [r] h, w xxxxxxxx xxxxxxxx 16-bit icu 0000dc h ipcp3 [r] h, w xxxxxxxx xxxxxxxx ipcp2 [r] h, w xxxxxxxx xxxxxxxx 0000e0 h ? ics23 [r/w] b, h, w 00000000 ? ics01 [r/w] b, h, w 00000000 0000e4 h occp1 [r/w] h, w xxxxxxxx xxxxxxxx occp0 [r/w] h, w xxxxxxxx xxxxxxxx 16-bit ocu *3 0000e8 h occp3 [r/w] h, w xxxxxxxx xxxxxxxx occp2 [r/w] h, w xxxxxxxx xxxxxxxx 0000ec h occp5 [r/w] h, w xxxxxxxx xxxxxxxx occp4 [r/w] h, w xxxxxxxx xxxxxxxx 0000f0 h occp7 [r/w] h, w xxxxxxxx xxxxxxxx occp6 [r/w] h, w xxxxxxxx xxxxxxxx 0000f4 h ocs23 [r/w] b, h, w 1110110 00001100 ocs01 [r/w] b, h, w 1110110 00001100 0000f8 h ocs67 [r/w] b, h, w 1110110 00001100 ocs45 [r/w] b, h, w 1110110 00001100 0000fc h ?? ? ? reserved 000100 h to 000114 h ?? ? ? reserved 000118 h gcn10 [r/w] h 00110010_00010000 ? gcn20 [r/w] b 00000000 ppg control 0 00011c h ?? reserved 000120 h ptmr0 [r] h, w 11111111_11111111 pcsr0 [w] h, w xxxxxxxx_xxxxxxxx ppg0 000124 h pdut0 [w] h, w xxxxxxxx_xxxxxxxx pcnh0 [r/w] b, h, w 00000000 pcnl0 [r/w] b, h, w 00000000 000128 h ptmr1 [r] h, w 11111111_11111111 pcsr1 [w] h, w xxxxxxxx_xxxxxxxx ppg1 00012c h pdut1 [w] h, w xxxxxxxx_xxxxxxxx pcnh1 [r/w] b, h, w 00000000 pcnl1 [r/w] b, h, w 00000000
mb91350a series 38 (continued) address register block diagram + 0 + 1 + 2 + 3 000130 h ptmr2 [r] h, w 11111111_11111111 pcsr2 [w] h, w xxxxxxxx_xxxxxxxx ppg2 000134 h pdut2 [w] h, w xxxxxxxx_xxxxxxxx pcnh2 [r/w] b, h, w 00000000 pcnl2 [r/w] b, h, w 00000000 000138 h ptmr3 [r] h, w 11111111_11111111 pcsr3 [w] h, w xxxxxxxx_xxxxxxxx ppg3 00013c h pdut3 [w] h, w xxxxxxxx_xxxxxxxx pcnh3 [r/w] b, h, w 00000000 pcnl3[r/w] b, h, w 00000000 000140 h ptmr4 [r] h, w 11111111_11111111 pcsr4 [w] h, w xxxxxxxx_xxxxxxxx ppg4 000144 h pdut4 [w] h, w xxxxxxxx_xxxxxxxx pcnh4 [r/w] b, h, w 00000000 pcnl4 [r/w] b, h, w 00000000 000148 h ptmr5 [r] h, w 11111111_11111111 pcsr5 [w] h, w xxxxxxxx_xxxxxxxx ppg5 00014c h pdut5 [w] h, w xxxxxxxx_xxxxxxxx pcnh5 [r/w] b, h, w 00000000 pcnl5 [r/w] b, h, w 00000000 000150 h to 0001fc h ? reserved 000200 h dmaca0 [r/w] b, h, w* 2 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000208 h dmaca1 [r/w] b, h, w* 2 00000000 0000xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] b, h, w* 2 00000000 0000xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] b, h, w* 2 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000220 h dmaca4 [r/w] b, h, w* 2 00000000 0000xxxx xxxxxxxx xxxxxxxx 000224 h dmacb4 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000228 h ?
mb91350a series 39 (continued) address register block diagram + 0 + 1 + 2 + 3 00022c h to 00023c h ? reserved 000240 h dmacr [r/w] b 0xx00000 xxxxxxxx xxxxxxxx xxxxxxxx dmac 000244 h to 00027c h ? reserved 000280 h frlr [r/w] b, h, w - - - - - - 01* 3 ??? f-bus ram capacity limit 000284 h to 00038c h ? reserved 000390 h drlr [r/w] b, h, w - - - - - - 01* 3 ??? d-bus ram capacity limit 000394 h to 0003ec h ? reserved 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h ddrg[r/w] b - - 000000 ddrh [r/w] b - - 000000 ddri [r/w] b - - 000000 ddrj [r/w] b 00000000 r-bus data direction register 000404 h ddrk [r/w] b 00000000 ddrl [r/w] b - - - - - - 00 ddrm [r/w] b - - 000000 ddrn [r/w] b - - 000000 000408 h ddro [r/w] b 00000000 ddrp [r/w] b - - - - 0000 ? 00040c h ? 000410 h pfrg [r/w] b - - 00 - 00 - pfrh [r/w] b - - 00 - 00 - pfri [r/w] b - - 00 - 00 - ? r-bus port function register 000414 h ________ pfrl [r/w] b - - - - - - 00 pfrm [r/w] b - - 00 - 00 - pfrn [r/w] b - - 000000 000418 h pfro [r/w] b 00000000 pfrp [r/w] b - - - - 0000 ? 00041c h ? reserved
mb91350a series 40 (continued) address register block diagram + 0 + 1 + 2 + 3 000420 h pcrg [r/w] b - - 000000 pcrh [r/w] b - - 000000 pcri [r/w] b - - 000000 ? r-bus pull-up control register 000424 h ?? pcrm [r/w] b - - 000000 pcrn [r/w] b - - 000000 000428 h pcro [r/w] b 00000000 pcrp [r/w] b - - - - 0000 ?? 00042c h to 00043c h ? reserved 000440 h icr00 [r/w] b, h, w - - - 11111 icr01 [r/w] b, h, w - - - 11111 icr02 [r/w] b, h, w - - - 11111 icr03 [r/w] b, h, w - - - 11111 interrupt control unit 000444 h icr04 [r/w] b, h, w - - - 11111 icr05 [r/w] b, h, w - - - 11111 icr06 [r/w] b, h, w - - - 11111 icr07 [r/w] b, h, w - - - 11111 000448 h icr08 [r/w] b, h, w - - - 11111 icr09 [r/w] b, h, w - - - 11111 icr10 [r/w] b, h, w - - - 11111 icr11 [r/w] b, h, w - - - 11111 00044c h icr12 [r/w] b, h, w - - - 11111 icr13 [r/w] b, h, w - - - 11111 icr14 [r/w] b, h, w - - - 11111 icr15 [r/w] b, h, w - - - 11111 000450 h icr16 [r/w] b, h, w - - - 11111 icr17 [r/w] b, h, w - - - 11111 icr18 [r/w] b, h, w - - - 11111 icr19 [r/w] b, h, w - - - 11111 000454 h icr20 [r/w] b, h, w - - - 11111 icr21 [r/w] b, h, w - - - 11111 icr22 [r/w] b, h, w - - - 11111 icr23 [r/w] b, h, w - - - 11111 000458 h icr24 [r/w] b, h, w - - - 11111 icr25 [r/w] b, h, w - - - 11111 icr26 [r/w] b, h, w - - - 11111 icr27 [r/w] b, h, w - - - 11111 00045c h icr28 [r/w] b, h, w - - - 11111 icr29 [r/w] b, h, w - - - 11111 icr30 [r/w] b, h, w - - - 11111 icr31 [r/w] b, h, w - - - 11111 000460 h icr32 [r/w] b, h, w - - - 11111 icr33 [r/w] b, h, w - - - 11111 icr34 [r/w] b, h, w - - - 11111 icr35 [r/w] b, h, w - - - 11111 000464 h icr36 [r/w] b, h, w - - - 11111 icr37 [r/w] b, h, w - - - 11111 icr38 [r/w] b, h, w - - - 11111 icr39 [r/w] b, h, w - - - 11111 000468 h icr40 [r/w] b, h, w - - - 11111 icr41 [r/w] b, h, w - - - 11111 icr42 [r/w] b, h, w - - - 11111 icr43 [r/w] b, h, w - - - 11111 00046c h icr44 [r/w] b, h, w - - - 11111 icr45 [r/w] b, h, w - - - 11111 icr46 [r/w] b, h, w - - - 11111 icr47 [r/w] b, h, w - - - 11111 000470 h to 00047c h ? 000480 h rsrr [r/w] b, h, w 10000000 stcr [r/w] b, h, w 00110011 tbcr [r/w] b, h, w 00xxxx00 ctbr [w] b, h, w xxxxxxxx clock control unit 000484 h clkr [r/w] b, h, w 00000000 wpr [w] b, h, w xxxxxxxx divr0 [r/w] b, h, w 00000011 divr1 [r/w] b, h, w 00000000 000488 h ?? osccr [r/w] b xxxxxxx0 ?
mb91350a series 41 (continued) address register block diagram + 0 + 1 + 2 + 3 00048c h wpcr [r/w] b 00 - - - 000 ??? clock timer 000490 h oscr [r/w] b 000 - - xx0 ??? main oscillation stabilization timer 000494 h rstop0 [w] b 00000000 rstop1 [w] b 00000000 rstop2 [w] b 00000000 rstop3 [w] b - - - - - 000 peripheral stop control 000498 h ???? reserved 00049c h to 0005fc h ? reserved 000600 h ?? ddr2 [r/w] b 00000000 ddr3 [r/w] b 00000000 t-unit data direction register 000604 h ddr4 [r/w] b 00000000 ddr5 [r/w] b 00000000 ddr6 [r/w] b 00000000 ? 000608 h ddr8 [r/w] b - - 000000 ddr9 [r/w] b - - - 00000 ddra [r/w] b - - - - 0000 ddrb [r/w] b 00000000 00060c h ddrc [r/w] b - - - - - 000 ? 000610 h ???? t-unit port function register 000614 h ?? pfr6 [r/w] b 11111111 ? 000618 h pfr8 [r/w] b - - 1 - - 0 - - pfr9 [r/w] b - - - 010 - 1 pfra [r/w] b - - - - 1111 pfrb1 [r/w] b 00000000 00061c h pfrb2 [r/w] b 00 - - - - 00 pfrc [r/w] b - - - 00000 ?? 000620 h ?? pcr2 [r/w] b 00000000 pcr3 [r/w] b 00000000 t-unit pull-up control register 000624 h pcr4 [r/w] b 00000000 pcr5 [r/w] b 00000000 pcr6 [r/w] b 00000000 ? 000628 h pcr8 [r/w] b --000000 pcr9 [r/w] b 00000000 pcra [r/w] b 00000000 pcrb [r/w] b 00000000 00062c h pcrc [r/w] b -----000 ??? 000630 h to 00063c h ? reserved 000640 h asr0 [r/w] h, w 00000000 00000000 acr0 [r/w] b, h, w 1111xx00 00000000 t-unit 000644 h asr1 [r/w] h, w 00000000 00000000 acr1 [r/w] b, h, w xxxxxxxx xxxxxxxx 000648 h asr2 [r/w] h, w 00000000 00000000 acr2 [r/w] b, h, w xxxxxxxx xxxxxxxx
mb91350a series 42 (continued) address register block diagram + 0 + 1 + 2 + 3 00064c h asr3 [r/w] h, w 00000000 00000000 acr3 [r/w] b, h, w xxxxxxxx xxxxxxxx t-unit 000650 h asr4 [r/w] h, w 00000000 00000000 acr4 [r/w] b, h, w xxxxxxxx xxxxxxxx 000654 h asr5 [r/w] h, w 00000000 00000000 acr5 [r/w] b, h, w xxxxxxxx xxxxxxxx 000658 h asr6 [r/w] h, w 00000000 00000000 acr6 [r/w] b, h, w xxxxxxxx xxxxxxxx 00065c h asr7 [r/w] h, w 00000000 00000000 acr7 [r/w] b, h, w xxxxxxxx xxxxxxxx 000660 h awr0 [r/w] b, h, w 01111111 11111111 awr1 [r/w] b, h, w xxxxxxxx xxxxxxxx 000664 h awr2 [r/w] b, h, w xxxxxxxx xxxxxxxx awr3 [r/w] b, h, w xxxxxxxx xxxxxxxx 000668 h awr4 [r/w] b, h, w xxxxxxxx xxxxxxxx awr5 [r/w] b, h, w xxxxxxxx xxxxxxxx 00066c h awr6 [r/w] b, h, w xxxxxxxx xxxxxxxx awr7 [r/w] b, h, w xxxxxxxx xxxxxxxx 000670 h ? 000674 h ? 000678 h iowr0 [r/w] b, h, w xxxxxxxx iowr1 [r/w] b, h, w xxxxxxxx iowr2 [r/w] b, h, w xxxxxxxx ? 00067c h ? 000680 h cser [r/w] b, h, w 00000001 ?? tcr [w] b, h, w 0000xxxx 000684 h to 000afc h ? reserved 000b00 h ests0 [r/w] x0000000 ests1 [r/w] xxxxxxxx ests2 [r] 1xxxxxxx ? dsu (evalua- tion chip only) 000b04 h ectl0 [r/w] 0x000000 ectl1 [r/w] 00000000 ectl2 [w] 000x0000 ectl3 [r/w] 00x00x11 000b08 h ecnt0 [w] xxxxxxxx ecnt1 [w] xxxxxxxx eusa [w] xxx00000 edtc [w] 0000xxxx
mb91350a series 43 (continued) address register block diagram + 0 + 1 + 2 + 3 000b0c h ewpt [r] 00000000 00000000 ? dsu (evaluation chip only) 000b10 h edtr0 [w] xxxxxxxx xxxxxxxx edtr1 [w] xxxxxxxx xxxxxxxx 000b14 h to 000b1c h ? 000b20 h eia0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b24 h eia1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b28 h eia2 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b2c h eia3 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b30 h eia4 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b34 h eia5 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b38 h eia6 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b3c h eia7 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b40 h edta [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b44 h edtm [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b48 h eoa0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b4c h eoa1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b50 h epcr [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b54 h epsr [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b58 h eiam0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b5c h eiam1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b60 h eoam0/eodm0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91350a series 44 (continued) address register block diagram + 0 + 1 + 2 + 3 000b64 h eoam1/eodm1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dsu (evaluation chip only) 000b68 h eod0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b6c h eod1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b70 h to 000bfc h ? reserved 000c00 h register access disallowed interrupt control unit 000c04 h to 000c14 h register access disallowed r-bus test 000c18 h to 000ffc h ? reserved 001000 h dmasa0 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx dmac 001004 h dmada0 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001008 h dmasa1 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 00100c h dmada1 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001010 h dmasa2 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001014 h dmada2 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001018 h dmasa3 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 00101c h dmada3 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001020 h dmasa4 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001024 h dmada4 [r/w] w xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx 001028 h to 001ffc h ? reserved
mb91350a series 45 (continued) *1 : test register access barred *2 : the lower 16-bit (dtc(15: 0)) of dmac a0 to dmaca4 cannot be accessed in byte. *3 : the available area of internal ram is restricted by the function described in 6-209 immediately after a reset is canceled. when the setting of the available area is updat ed, the instruction must be followed by at least 1 nop instruction. address register block diagram + 0 + 1 + 2 + 3 007000 h flcr [r/w] 0110x000 ??? flash memory 007004 h flwc [r/w] 00010011 ??? 007008 h ???? 00700c h ???? 007010 h ???? 007014 h to 0070ff h ? reserved
mb91350a series 46 vector table (continued) interrupt source interrupt number interrupt level offset tbr default address rn 10 16 reset 0 00 ? 3fc h 000ffffc h ? mode vector 1 01 ? 3f8 h 000ffff8 h ? system reserved 2 02 ? 3f4 h 000ffff4 h ? system reserved 3 03 ? 3f0 h 000ffff0 h ? system reserved 4 04 ? 3ec h 000fffec h ? system reserved 5 05 ? 3e8 h 000fffe8 h ? system reserved 6 06 ? 3e4 h 000fffe4 h ? coprocessor absent trap 7 07 ? 3e0 h 000fffe0 h ? coprocessor error trap 8 08 ? 3dc h 000fffdc h ? inte instruction 9 09 ? 3d8 h 000fffd8 h ? instruction break exception 10 0a ? 3d4 h 000fffd4 h ? operand break trap 11 0b ? 3d0 h 000fffd0 h ? step trace trap 12 0c ? 3cc h 000fffcc h ? nmi request (tool) 13 0d ? 3c8 h 000fffc8 h ? undefined instruction exception 14 0e ? 3c4 h 000fffc4 h ? nmi request 15 0f 15 (f h ) fixed15 3c0 h 000fffc0 h ? external interrupt 0 16 10 icr00 3bc h 000fffbc h 6 external interrupt 1 17 11 icr01 3b8 h 000fffb8 h 7 external interrupt 2 18 12 icr02 3b4 h 000fffb4 h 11 external interrupt 3 19 13 icr03 3b0 h 000fffb0 h ? external interrupt 4 20 14 icr04 3ac h 000fffac h ? external interrupt 5 21 15 icr05 3a8 h 000fffa8 h ? external interrupt 6 22 16 icr06 3a4 h 000fffa4 h ? external interrupt 7 23 17 icr07 3a0 h 000fffa0 h ? reload timer 0 24 18 icr08 39c h 000fff9c h 8 reload timer 1 25 19 icr09 398 h 000fff98 h 9 reload timer 2 26 1a icr10 394 h 000fff94 h 10 uart(reception completed) 27 1b icr11 390 h 000fff90 h 0 uart(reception completed) 28 1c icr12 38c h 000fff8c h 1 uart(reception completed) 29 1d icr13 388 h 000fff88 h 2 uart0 (rx completed) 30 1e icr14 384 h 000fff84 h 3 uart1 (rx completed) 31 1f icr15 380 h 000fff80 h 4 uart2 (rx completed) 32 20 icr16 37c h 000fff7c h 5
mb91350a series 47 (continued) interrupt source interrupt number interrupt level offset tbr default address rn 10 16 dmac0 (end, error) 33 21 icr17 378 h 000fff78 h ? dmac1 (end, error) 34 22 icr18 374 h 000fff74 h ? dmac2 (end, error) 35 23 icr19 370 h 000fff70 h ? dmac3 (end, error) 36 24 icr20 36c h 000fff6c h ? dmac4 (end, error) 37 25 icr21 368 h 000fff68 h ? a/d 38 26 icr22 364 h 000fff64 h 15 i 2 c 39 27 icr23 360 h 000fff60 h ? uart4 (reception completed) 40 28 icr24 35c h 000fff5c h ? sio 5 41 29 icr25 358 h 000fff58 h 12 sio 6 42 2a icr26 354 h 000fff54 h 13 sio 7 43 2b icr27 350 h 000fff50 h 14 uart3 (reception completed) 44 2c icr28 34c h 000fff4c h ? uart3 (rx completed) 45 2d icr29 348 h 000fff48 h ? reload timer 3/main oscillation stabilization wait timer 46 2e icr30 344 h 000fff44 h ? timebase timer overflow 47 2f icr31 340 h 000fff40 h ? external interrupt: fpint(8-15) 48 30 icr32 33c h 000fff3c h ? clock counter 49 31 icr33 338 h 000fff38 h ? u/d counter0 50 32 icr34 334 h 000fff34 h ? u/d counter1 51 33 icr35 330 h 000fff30 h ? ppg 0/1 52 34 icr36 32c h 000fff2c h ? ppg 2/3 53 35 icr37 328 h 000fff28 h ? ppg 4/5 54 36 icr38 324 h 000fff24 h ? 16-bit free-run timer 55 37 icr39 320 h 000fff20 h ? icu2/3 (capture) 56 38 icr40 31c h 000fff1c h ? icu1 (capture)/uart4 (transmission complete) 57 39 icr41 318 h 000fff18 h ? icu0 (capture) 58 3a icr42 314 h 000fff14 h ? ocu0/1 (match) 59 3b icr43 310 h 000fff10 h ? ocu2/3 (match) 60 3c icr44 30c h 000fff0c h ? ocu4/5 (match) 61 3d icr45 308 h 000fff08 h ? ocu6/7 (match) 62 3e icr46 304 h 000fff04 h ? interrupt delay source bit 63 3f icr47 300 h 000fff00 h ? system reserved (used by realos) 64 40 ? 2fc h 000ffefc h ? system reserved (used by realos) 65 41 ? 2f8 h 000ffef8 h ?
mb91350a series 48 (continued) interrupt source interrupt number interrupt level offset tbr default address rn 10 16 system reserved 66 42 ? 2f4 h 000ffef4 h ? system reserved 67 43 ? 2f0 h 000ffef0 h ? system reserved 68 44 ? 2ec h 000ffeec h ? system reserved 69 45 ? 2e8 h 000ffee8 h ? system reserved 70 46 ? 2e4 h 000ffee4 h ? system reserved 71 47 ? 2e0 h 000ffee0 h ? system reserved 72 48 ? 2dc h 000ffedc h ? system reserved 73 49 ? 2d8 h 000ffed8 h ? system reserved 74 4a ? 2d4 h 000ffed4 h ? system reserved 75 4b ? 2d0 h 000ffed0 h ? system reserved 76 4c ? 2cc h 000ffecc h ? system reserved 77 4d ? 2c8 h 000ffec8 h ? system reserved 78 4e ? 2c4 h 000ffec4 h ? system reserved 79 4f ? 2c0 h 000ffec0 h ? used by int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h ?
mb91350a series 49 peripheral resources 1. interrupt controller (1)description the interrupt controller manages in terrupt reception and arbitration. hardware configuration this module consists of the following components: icr register interrupt priority determination circuit interrupt level and interrupt number (vector) generator hold request cancellation request generator main function this module has the following major functions: detect nmi and interrupt requests prioritize interrupts (accor ding to level and number) notify interrupt level of selected interrupt request (to cpu) notify interrupt number of selected interrupt request (to cpu) request (to the cpu) to return from stop mode in response to an nmi or in terrupt request with interrupt level other than ?11111? hold request cancellation r equest issued to the bus master (2)register list (continued) icr register 765432 1 0 icr00 ??? icr4 icr3 icr2 icr1 icr0 icr01 ??? icr4 icr3 icr2 icr1 icr0 icr02 ??? icr4 icr3 icr2 icr1 icr0 icr03 ??? icr4 icr3 icr2 icr1 icr0 icr04 ??? icr4 icr3 icr2 icr1 icr0 icr05 ??? icr4 icr3 icr2 icr1 icr0 icr06 ??? icr4 icr3 icr2 icr1 icr0 icr07 ??? icr4 icr3 icr2 icr1 icr0 icr08 ??? icr4 icr3 icr2 icr1 icr0 icr09 ??? icr4 icr3 icr2 icr1 icr0 icr10 ??? icr4 icr3 icr2 icr1 icr0 icr11 ??? icr4 icr3 icr2 icr1 icr0 icr12 ??? icr4 icr3 icr2 icr1 icr0 icr13 ??? icr4 icr3 icr2 icr1 icr0 icr14 ??? icr4 icr3 icr2 icr1 icr0 icr15 ??? icr4 icr3 icr2 icr1 icr0
mb91350a series 50 (continued) hold request cancel request resister (hrcl) 7654321 0 icr16 ??? icr4 icr3 icr2 icr1 icr0 icr17 ??? icr4 icr3 icr2 icr1 icr0 icr18 ??? icr4 icr3 icr2 icr1 icr0 icr19 ??? icr4 icr3 icr2 icr1 icr0 icr20 ??? icr4 icr3 icr2 icr1 icr0 icr21 ??? icr4 icr3 icr2 icr1 icr0 icr22 ??? icr4 icr3 icr2 icr1 icr0 icr23 ??? icr4 icr3 icr2 icr1 icr0 icr24 ??? icr4 icr3 icr2 icr1 icr0 icr25 ??? icr4 icr3 icr2 icr1 icr0 icr26 ??? icr4 icr3 icr2 icr1 icr0 icr27 ??? icr4 icr3 icr2 icr1 icr0 icr28 ??? icr4 icr3 icr2 icr1 icr0 icr29 ??? icr4 icr3 icr2 icr1 icr0 icr30 ??? icr4 icr3 icr2 icr1 icr0 icr31 ??? icr4 icr3 icr2 icr1 icr0 icr32 ??? icr4 icr3 icr2 icr1 icr0 icr33 ??? icr4 icr3 icr2 icr1 icr0 icr34 ??? icr4 icr3 icr2 icr1 icr0 icr35 ??? icr4 icr3 icr2 icr1 icr0 icr36 ??? icr4 icr3 icr2 icr1 icr0 icr37 ??? icr4 icr3 icr2 icr1 icr0 icr38 ??? icr4 icr3 icr2 icr1 icr0 icr39 ??? icr4 icr3 icr2 icr1 icr0 icr40 ??? icr4 icr3 icr2 icr1 icr0 icr41 ??? icr4 icr3 icr2 icr1 icr0 icr42 ??? icr4 icr3 icr2 icr1 icr0 icr43 ??? icr4 icr3 icr2 icr1 icr0 icr44 ??? icr4 icr3 icr2 icr1 icr0 icr45 ??? icr4 icr3 icr2 icr1 icr0 icr46 ??? icr4 icr3 icr2 icr1 icr0 icr47 ??? icr4 icr3 icr2 icr1 icr0 7 6543210 hrcl mhalt1 ?? lvl4 lvl3 lvl2 lvl1 lvl0
mb91350a series 51 (3)block diagram r i00 5 6 level4 to level 0 mhalti vct5 to vct0 r-bus unmi wakeup icr00 nmi ("1" when level 11111) determine order of priority level determination vector determination level, vector genera- tion hldreq cancel nmi request
mb91350a series 52 2. external interrupt/nmi control (1)description the external interrupt control unit is the block that controls external interrupt requests input to nmi and int0 to int15. the level can be selected from ?h?, ?l?, ri sing edge, or falling edge (except for nmi). (2)register list (3)blockdiagram external interrupt enable register (enir) external interrupt re quest register (eirr) request level setting register (elvr) the above registers (for 8 channe ls) are available in two sets; there are a total of 16 channels. 76543210 en6 en7 en5 en4 en3 en2 en1 en0 15 14 13 12 11 10 9 8 er6 er7 er5 er4 er3 er2 er1 er0 15 14 13 12 11 10 9 8 la7 lb7 lb6 la6 lb5 la5 lb4 la4 76543210 la3 lb3 lb2 la2 lb1 la1 lb0 la0 17 17 int0 to int1 5 nmi 8 8 16 r-bus interrupt request interrupt enable register gate request f/f edge detection circuit interrupt source register interrupt level setting register
mb91350a series 53 3. realos-related hardware realos-related hardware is used by the real-time os. therefore, realos-related hardware cannot be used by user programs when realos is used. ? delay interrupt module (1)description the delayed interrupt module generates a task switching interrupt. this module enables software to issue or cancel an interrupt request to the cpu. (2)register list (3)block diagram delayed interrupt control register (dicr) 76543210 ??????? dly1 dlyi r-bus interrupt request
mb91350a series 54 ? bit search module (1)description the bit search module searches data written to an input register for ?0?, ?1?, or a change point and returns the detected bit position. (2)register list (3)block diagram 31 0 0 detection data register (bsd0) 1 detection data register (bsd1) data register for transition detection (bsdc) detection result register (bsrr) d -bus address decoder input latch detection mode creating 1 detection data bit search circuit search results
mb91350a series 55 4. 8/16-bit up/down counter (1)description this block is the up/down counter co nsisting of 6 event input pins, an 8/ 16-bit up/down counter, an 8-bit reload/ compare register, and their control circuit. the MB91F355A/mb91355a/mb91354a/mb91 v350a contain 2 channels of 8/16 -bit up/down counter in this block. this module has the following features. 8-bit count register enabling counting from (0)d to ( 255)d (enabling counting from (0 )d to (65535)d in "16-bit x 1 operation mode" ). four different count modes available with selectable count clocks capable of selecting a count clock signal in timer mode, from among the inputs from two internal clocks and an internal circuit capable of selecting the detecti on edge of the external pin input signal in up/down counter mode phase difference count mode suitable for counting for an encoder such as a motor, capable of easily counting the rotation angle and the number of revolutions at hi gh precision by inputti ng the phase-a, phase-b, and phase-z outputs of the encoder zin pin available for two functions selectable (valid in all modes) compare and reload functions availabl e not only separately but also in combination for up/down counting at an arbitrary width count direction flag used to i dentify the preceding count direction capable of controlling the independent generations of interrupts at a compare match, reload (underflow), overflow, or at a count direction change count mode timer mode up/down counter mode phase difference count mode (2 multiplication) phase difference count mode (4 multiplication) count clock 80 ns (12.5 mhz : 2-frequency division) (when operating at 25 mhz ) 320 ns (3.125 hz : 8-frequency division) detection edge falling edge detection rising edge detection detection at rising edge, falling edge, or both edges edge detection disabled zin pin counter clear function gate function compare/reload function compare function (comparison interrupt request output) compare function (comparison interrupt request output and counter clear) reload function (underflow inte rrupt request output and reload) compare/reload function(comparison in terrupt request output and counter clear; underflow interrupt request output and reload) compare/reload disabled
mb91350a series 56 (2)register list 2.1 up/down count resister (udcr) up/down count resister ch0 (udcr0) up/down count resister ch1 (udcr1) 2.2 reload compare resister (rcr) reload compare resister ch0 (rcr0) reload compare resister ch1 (rcr1) 2.3 counter status register (csr) counter status register ch(0, 1) (csr0, 1) 2.4 counter control resister (ccrl) counter control resister ch(0, 1) (ccrl0, 1) 2.5 counter control resister (ccrh) counter control resister ch0 (ccrh0) 2.6 counter control resister ch1 (ccrh1) 7 6543210 d06 d07 d05 d04 d03 d02 d01 d00 15 14 13 12 11 10 9 8 d14 d15 d13 d12 d11 d10 d09 d08 7 6543210 d06 d07 d05 d04 d03 d02 d01 d00 15 14 13 12 11 10 9 8 d14 d15 d13 d12 d11 d10 d09 d08 7 6543210 cit cst udi cm ovf ud ud ud 7 6543210 ctu uc rld ud cgs cge cge reserved 15 14 13 12 11 10 9 8 cdc m16 cfi clk cm cm ces ces 15 14 13 12 11 10 9 8 cdc cfi clk cm cm ces ces reserved
mb91350a series 57 (3)block diagram cge cge cgs ctu uc ud ces ces cm clk ain0, ain1 z in0, zin1 bin0, bin1 cm cst ud ud cdc ud ovf cm m16 car ry udi cit cfi rld 8 bit 8 bit data bus edge/level detection up/down count clock select prescaler udcr0(up/down counter register ch0 counter clear reload control rcr0(reload compare register ch0 interrupt output to ch1 count clock
mb91350a series 58 5. 16-bit reload timer (1)description the 16-bit timer consists of a 16-bit do wn counter, 16-bit reload register, internal clock, clock generation prescaler, and control register. the clock source can be selected from among three inte rnal clocks (prepared by frequency dividing the machine clock by 2/8/32, and also by 64/128 only for ch3) and an external event. the interrupt can be used to initiate dma transfer. the MB91F355A/mb91355a/mb91354a/mb91v350a contain 4 channels of this timer. (2)register list control status register (tmcsr) 16-bit timer register(tmr) 16-bit reload register(tmrlr) (ch3 only) 15 14 13 12 11 10 9 8 ? ? csl2 csl1 csl0 reserved reserved reserved 7 6543210 ? outl reld inte uf cnte trg reserved 15 0 15 0
mb91350a series 59 (3)block diagram reld outl inte uf cnte trg out ctl. csl2 csl1 csl0 16 7 16 3 in ctl. toe0 to 3 2 2 2 1 35 exck ir q 2 2 6 7 r | b u s 16-bit reload register (tmrlr) 16-bit timer register (tmr) uf reload clock selector re-trigger prescaler clear machine clock input bit in pfrp count enable (ch3 only) external timer output (tot0 to tot3)
mb91350a series 60 6. ppg (programable pulse generator) the ppg can efficiently output highly precise pwm waveforms. the MB91F355A/mb91355a/mb91354a/mb91v35 0a contain 6 channels of ppg timer. (1)description each channel consists of a 16-bit down counter, 16-bi t data register with cycle setting buffer, 16-bit compare register with duty ratio setting buffer, and pin control unit. the count clocks for the 16-bit down counter can be se lected from the following 4 types :(peripheral clock , / 4, /16, /64) the counter is initialized to "ffff h " at a reset or counter borrow. ppg outputs (ppg0 to ppg5) are provided for each channel. (2)register list (3)block diagram (overall configuration for 1 channel) 15 0 general control register 10 (gcn10) general control register 20 (gcn20) timer register (ptmr0 to 5) cycle setting register (pcsr0 to 5) duty setting register (pdut0) 4 ppg 0 ppg 4 ppg 2 ppg 1 ppg 5 ppg 3 16-bit reload timer ch0 16-bit reload timer ch1 general d/a control icr register 20 general d/a control icr register 10 (resource select) trg input ppg timer ch4 trg input ppg timer ch2 external trg0 to trg3 trg input ppg timer ch1 trg input ppg timer ch3 trg input ppg timer ch5 trg input ppg timer ch0 external trg4 external trg5
mb91350a series 61 7. u-timer (16-bit timer for uart baud rate generation) (1) description the u-timer is a 16-bit timer for generating the baud ra te for the uart. an arbitrary baud rate can be set depending on the combination of the chip opera ting frequency and u-timer reload value. the MB91F355A/mb91355a/mb91354a/mb91v350a contain 5 channels of this timer. (2) register list (3) block diagram 15 8 7 0 u-timer register (utim) reload register (utimr) u-timer control register (utimc) utimr (reload register) utim (u-timer) clock load underflow to uart control f.f. 15 15 0 0 (peripheral clock)
mb91350a series 62 8. uart (1) description the uart is a serial i/o port for asynchronous (start-stop) or clk sy nchronous communication. this module has the features listed below. the MB91F355A/mb91355a /mb91354a/mb91v350a contain 5 channels of uart. full duplex double buffer asynchronous (start-stop synchronize d) or clk synchronized transmission supports multi-processor mode completely programmable baud rate. arbitrary baud rate set by built-in timer (see the section for "u-timer?.) variable baud rate can be input from an external clock. error detection functions(parity, framing, overrun) transmission signal format is nrz uart ch0 to ch2 can start dma transfer using in terrupts (ch3 and ch4 c annot start dma transfer). capable of clearing dmac interrupt source by writing to drcl register (2)register list serial input register/serial output register (sidr/sodr) serial status register(ssr) serial mode register serial control register(scr) decl register (drcl) 76543210 d6 d7 d5 d4 d3 d2 d1 d0 76543210 ore pe fre rdrf tdre bds rie tie 76543210 md0 md1 ?? cs0 ??? 76543210 p pen sbl cl a/d rec rxe txe 76543210 ? ???????
mb91350a series 63 (3) block diagram md1 md0 cs0 pen p sbl cl a / d rec rxe txe pe ore fre rdrf tdre bds rie tie r - bus sidr sodr control signal from u-timer external clock sck clock selection circuit receive status decision circuit for dma received error generating signal (to dmac) reception clock reception control circuit start bit detection circuit received bit counter received parity counter rx shifter rx complete transmission clock rx interrupt (to cpu) tx interrupt (to cpu) transmission control circuit transmission start circuit sending bit counter sending parity counter tx shifter start transmis- sion smr register control signal scr register ssr register sck (clock) si (receive data) so (send data)
mb91350a series 64 9. extended i/o serial interface (sio) (1) description this block is a serial i/o interface that allows data tr ansfer using clock synchronization. it is composition of a single 8-bit 1 channel. lsb-first or msb-first transfer mode can be selected for data transfer. the MB91F355A/mb91355a/mb91354a/mb91v35 0a contain 3 channels of this sio. the serial i/o interface operates in 2 modes: internal shift clock mode: transfer data in synchronization with the internal clock. external shift clock mode: transfer data in synchronizati on with the clock supplied via the external pin (sck). by manipulating the general-purpose port sh aring the external pin (sck) in this mode, data can also be transf erred by a cpu instruction. (2) register list serial mode control status register (smcs) sio test resister(ses) sdr (serial data register) sio prescaler control register (cdcr) dmac interrupt source clear register (srcl) 15 14 13 12 11 10 9 8 smd1 smd2 smd0 sie sir busy stop strt 76543210 ? ??? mode bds ?? 15 14 13 12 11 10 9 8 ? ????? tst1 tst0 76543210 d6 d7 d5 d4 d3 d2 d1 d0 15 14 13 12 11 10 9 8 ? md ?? div3 div2 div1 div0 76543210 ? ???????
mb91350a series 65 (3)block diagram si5 to si7 so5 to so7 s ck5 to sck7 smd2 smd1 smd0 sie sir busy stop strt mode bds 21 0 sce (msb fast) d0 to d7 (msb fast) d0 to d7 sdr (serial data register) internal clock internal data bus select transmitting direction read write control circuit shift clock counter interrupt request internal data bus initial value pfr register
mb91350a series 66 10. 16-bit free-run timer (1)description the 16-bit free-running timer consists of a 16-bit up co unter, control register, and status register. the count values of this timer are used as the base time r for the output compares and input capture modules. four count clock frequencies are available. an interrupt can be generated at a counter overflow. the counter can be initialized upon a match with compare register 0 of the output compare unit, depending on the mode. (2)register list (3)block diagram timer data register (upper) (tcdt) timer data register (lower) (tcdt) timer control status register (lower) (tccs) 15 14 13 12 11 10 9 8 t14 t15 t13 t12 t11 t10 t9 t8 76543210 t06 t07 t05 t04 t03 t02 t01 t00 76543210 ivf eclk ivfe stop mode clr clk1 clk0 eclk ivf ivfe stop mode clr clk1 clk0 frc k r-bus interrupt timer data register (tcdt) divider clock select to internal circuit (t15 to t00) comparator 0 clock
mb91350a series 67 11. input capture (1) description this module detects a rising or falling edge or both edges of an external i nput signal and stores the 16-bit free- running timer value in a register. this module stores the 16-bit free-running timer val ue in a register. in addition, the module can generate an interrupt upon detection of an edge. the input capture module consists of input capture data registers and a control register. each input capture unit has a co rresponding external input pin. the detection edge of an external input can be selected from among 3 types. rising edge falling edge both edges an interrupt can be generated upon detection of a valid edg e of an external input. (2) register list input capture data register (upper) (ipcp) input capture data register (lower) (ipcp) capture control register (ics23) capture control register (ics01) 15 14 13 12 11 10 9 8 cp14 cp15 cp13 cp12 cp11 cp10 cp09 cp08 76543210 cp06 cp07 cp05 cp04 cp03 cp02 cp01 cp00 76543210 icp2 icp3 ice3 ice2 eg31 eg30 eg21 eg20 76543210 icp0 icp1 ice1 ice0 eg11 eg10 eg01 eg00
mb91350a series 68 (3) block diagram eg11 eg10 eg01 eg00 eg31 eg30 eg21 eg20 icp1 icp0 ice1 ice0 icp3 icp2 ice3 ice2 r-bus 16-bit timer counter value (t15 to t00) input capture data register ch (0, 2) 16-bit timer counter value (t15 to t00) input capture data register ch (1, 3) edge detection edge detection in0, in2 input pin in1, in3 input pin interrupt interrupt
mb91350a series 69 12. output compare (1) description the output compare module consists of 16-bit compare registers, compare output latch, and control register. when the 16-bit free-running timer value matches the compare register value, the output level is inverted and an interrupt is issued. the MB91F355A/mb91355a/mb91354a/mb91v350a contain 8 channels of this block. this module has the features listed below. capable of using the 8 compare regi sters independently. output pins and interrupt flags corresponding to the compare registers a pair of compare registers can be used to control output pins. using tow compare registers to invert output pins capable of setting the initia l value for each output pin. interrupts can be generat ed upon a compare match. the ch0 compare register is used as the compare clear register for the 16-bit free-running timer. (2)register list output compare register(upper) (occp) output compare register(lower) (occp) output control register(upper) (ocs) output control register(lower) (ocs) 15 14 13 12 11 10 9 8 c14 c15 c13 c12 c11 c10 c09 c08 76543210 c06 c07 c05 c04 c03 c02 c01 c00 15 14 13 12 11 10 9 8 ? ?? cmod ?? otd1 otd0 76543210 icp0 icp1 ice1 ice0 ?? cst1 cst0
mb91350a series 70 (3) block diagram icp1 icp0 ice1 ice0 otd1 otd0 cst1 cst0 cmod ote0, ote2, ote4, ote6 r-bus ote1, ote3, ote5, ote7 (only ch0 is used as a free running timer clear register.) output compare register compare circuit output compare register compare circuit 16-bit free-run timer interrupt output compare output latch compare output latch ote0 and ote7 exist in pfro. there is in pfro. output interrupt output output
mb91350a series 71 13. i 2 c interface (1) description the i 2 c interface is a serial i/o port supporting the inte r-ic bus, operating as a mast er/slave device on the i 2 c bus. it has the following features master/slave sending and receiving arbitration function clock sync function slave address and general ca ll address detection function ditecting function of transmitting direction repeated start condition generati on and detection function bus error detection function 10-bit/7-bit slave address slave address receive acknowledge control when in master mode support for composite slave addresses capable of interruption when a transmission or bus error occurs standard mode (max 100k bps)/high speed mode (max 400k bps) supported
mb91350a series 72 (2)register list bus control register(ibcr) bus status register(ibsr) 10-bit slave address resister (itba) 10-bit slave address mask resister(itmk) 7-bit slave address resister (isba) 7-bit slave address mask resister (ismk) data register (idar) clock control register (iccr) clock disable register (idbl) 15 14 13 12 11 10 9 8 ber beie scc mss ack gcaa inte int 76543210 bb rsc al lrb trx aas gca adt 15 14 13 12 11 10 9 8 ?????? ta9 ta8 76543210 ta7 ta6 ta5 ta4 ta3 ta2 ta1 ta0 15 14 13 12 11 10 9 8 entb ral ???? tm9 tm8 76543210 tm7 tm6 tm5 tm4 tm3 tm2 tm1 tm0 76543210 ? sa6 sa5 sa4 sa3 sa2 sa1 sa0 15 14 13 12 11 10 9 8 ensb sm6 sm5 sm4 sm3 sm2 sm1 sm0 76543210 d7 d6 d5 d4 d3 d2 d1 d0 15 14 13 12 11 10 9 8 test ? en cs4cs3cs2cs1cs0 76543210 ??????? dbl
mb91350a series 73 (3) block diagram iccr en idbl dbl iccr ibsr bb rsc lrb last bit trx adt al ibcr ber beie inte int ibcr scc mss ack gcaa ibsr ismk itmk idar aas gca fnsb entb ral itba itmk isba ismk cs4 cs3 cs2 cs1 cs0 2345 32 sync clkp first byte irq scl i scl o sda sda o operation enable clock enable clock divide 2 clock selector2 (1/12) bus busy start sending/ receiving start stop condition generation arbitration lost detection interrupt request start master ack enable ack enable slave global call slave address compare end error shift clock edge changing timing start stop condition detection generating shift clock r-bus
mb91350a series 74 14. a/d converter (1) description the a/d converter converts the analog input voltage into a digital value. it has the following features: conversion time: 1.48 s minimum per channel employing serial/parallel conversion type for sample & hold circuit 10-bit resolution (switchable between 8 and 10 bits) program selection of the ana log input from among 12 channels conversion mode single conversion mode : convert 1 selected channel scan conversion mode : scan up to 4 channels. converted data is stored in the data buffer. an interrupt request to the cpu ca n be generated upon completion of a/ d conversion. the interrupt can be used to start dma transfer. the startup source can be selected from among software , external trigger (falling edge), and reload timer ch2 (rising edge). (2) register list adcs1 adcs2 15 0 adtl0 adth0 adtl2 adtl1 adth1 adth2 adtl3 adth3 87 control status register (adcs2/adsc1) conversion time setting resister (adct) converted data register 0 (adth0/adtl0) converted data register 1 (adth1/adtl1) converted data register 2 (adth2/adtl2) converted data register 3 (adth3/adtl3)
mb91350a series 75 (3) block diagram av cc , avrh, av ss /avrl a n0 a n1 a n2 a n3 a n4 a n5 a n6 a n7 a n8 a n9 a n10 a n11 m p x m p x s/h adt0 adt1 adt2 adt3 10 bit a/d converter r-bus control logic interrupt 16-bit reload timer ch2 external input analog input
mb91350a series 76 15. 8-bit d/a converter (1) description this block contains 2 channels of 8-bit d/a converters. the d/a converter register can be used to control the independent output of each channel. th e block has the following features. power saving function 3.3 v interface (2) register list (3) block diagram d/a data register 0 to 2(dadr0 to dadr2) d/a control register 0 to 2 (dacr0 to dacr2) 76543210 da6 da7 da5 da4 da3 da2 da1 da0 76543210 ? ?????? dae dae0 pd r-bus dae1 stop stop pd d/a d/a dae2 stop pd d/a d/a control d/a converter d/a converter d/a output 0 d/a output 1 d/a converter d/a output 2
mb91350a series 77 16. dmac (dma controller) (1) description this module realize direct memory access (d ma) transfer with the fr family device. dma transfer controlled by this module enables many types of data transfer to be performed at high speed without cpu intervention, thereby improving system performance. hardware configuration this model consists mainly of the following components: independent dma channels 5 channels 5 channels independent access control circuits 32-bit address register (suppo rts reloading: 2 per channel) 16-bit transfer count register (supports reloading: 1 per channel) 4-bit block count register (1 per channel) external transfer request input pins: dr eq0, dreq1, dreq2 (ch0, ch1, ch2 only) external transfer request acceptance output pins: dack0, dack1, dack2 (ch0, ch1,ch2 only) dma end output pins: deop0, deop 1, deop2 (ch0, ch1, ch2 only) (ch3 only) fly-by transfer (memory to i/o, i/o to memory) 2-cycle transfer main function this module has the following ma jor functions for data transfer: supports independent data transfer fo r multiple channels (5 channels) (1) priority order (ch0 > ch1 > ch2 > ch3 > ch4) (2) order can be reversed for ch0 and ch1 (3) dmac activation triggers external dedicated pin input (edge detect ion/level detection: ch0 to ch2 only) internal peripheral request (interrupt requ est sharing, including external interrupts) software request (register write) (4) transmission mode demand transfer, burst transfer, step transfer, or block transfer addressing mode: 32-bit full addressi ng (increment, decrement, or fixed) (address increment can be in the range - 255 to + 255) data length: byte, halfword, or word single-shot or reload operation selectable
mb91350a series 78 (2) register description 31 16 15 0 ch0 control/status register a (dmaca0) register b (dmacb0) ch1 control/status register a (dmaca1) register b (dmacb1) ch2 control/status register a (dmaca2) register b (dmacb2) ch3 control/status register a (dmaca3) register b (dmacb3) ch4 control/status register a (dmaca4) register b (dmacb4) overall control register (dmacr) ch0 transfer source address register (dmasa0) (dmada0) ch1 transfer source address register (dmasa1) (dmada1) ch2 transfer source address register (dmasa2) (dmada2) ch3 transfer source address register (dmasa3) (dmada3) ch4 transfer source address register (dmasa4) (dmada4)
mb91350a series 79 (3) block diagram read write ddno blk register ddno register dtcr dss [3:0] erir, edir type, mod, ws irq [4:0] mclre q x-bus dadm, dasz [7:0] dadr sadm, sasz [7:0] sadr dma transfer request to bus controller read/write control t o bus con- troller bus control block access address address counter counter buffer counter buffer selector selector write back selector buffer counter selector write back dtc two-stage register buffer counter selector dma start source select circuit & request acceptance control priority circuit status transition circuit dma control dsad two-stage register ddad two-stage register bus control block peripheral start request/ stop input external pin start request/stop input to interrupt controller clear peripheral interrupt 5-channel dmac block diagram write back
mb91350a series 80 electrical characteristics 1. abusolute maximum rating *1 : the parameter is based on v ss = da vs = av ss = 0 v. *2 : v cc must not be lower than v ss - 0.3 v. *3 : be careful not to exceed "v cc + 0.3 v?, for example, when the power is turned on. *4 : the maximum output current is the peak value for a single pin. *5 : the average output current is the average curr ent for a single pin over a period of 100 ms. *6 : the total average output curr ent is the average current for all pins over a period of 100 ms. parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.5 v ss + 4.0 v *2 analog power supply voltage* 1 da vc v ss ? 0.5 v ss + 4.0 v *3 analog power supply voltage* 1 av cc v ss ? 0.5 v ss + 4.0 v *3 analog reference voltage* 1 avrh v ss ? 0.5 v ss + 4.0 v *3 input voltage* 1 v i v ss ? 0.5 v cc + 0.5 v *8 input voltage (nch open-drain) * 1 v ind v ss ? 0.5 v ss + 5.5 v *8 analog pin input voltage* 1 v ia v ss ? 0.5 av cc + 0.5 v *8 output voltage* 1 v o v ss ? 0.5 v cc + 0.5 v maximum clamp current i clamp ? 2.0 + 2.0 ma *7 total maximum clamp current |i clamp | ? 20 ma *7 ?l? level maximum output current i ol ? 10 ma *4 ?h? level maximum output current (nch open-drain) i olnd ? 20 ma ?l? level average output current i olav ? 8ma*5 ?h? level average output current (nch open-drain) i olavnd ? 15 ma ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma *6 ?h? level maximum output current i oh ? ? 10 ma *4 ?h? level average output current i ohav ? ? 4ma*5 ?h? level total maximum output current i oh ? ? 50 ma ?h? level total average output current i ohav ? ? 20 ma *6 power consumption p d ? 850 mw operating temperature t a ? 40 + 85 c storage temperature t stg ? + 125 c
mb91350a series 81 *7 : ? relevant pins: port2, 3, 4, 5, 6, 8, 9, a, b, c, g, h, i, j, k, m, n, o, p, and an (a/d input) ? use within recommended operating conditions. ? use at dc voltage (current). ? the + b signal should always be applied a limitin g resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so t hat when the + b signal is applied the input current to the microcontroller pin does not exceed rated va lues, either instantaneously or for prolonged periods. ? note that, when the microcontroller drive current is low as in low po wer consumption mode, the + b input potential can incr ease the potential at the v cc pin via a protective diode, possibly affecting other devices. ? note that, if the + b input exists when the microcontro ller is off (not fixed at 0 v), power is supplied through the pin, possibly causing t he microcontroller to operate imperfectly. ? note that, if the + b input exists when the power supply is turned on, power is supplied through the pin, possibly resulting in a power-supply vo ltage at which a power-on reset does not work. ? be careful not to le t the + b input pin open. ? note that the analog i/o pins (such as the lcd drive and comparator input pins) other than the a/d input pin cannot input + b. ? sample recommended circuits: *8: v i should not exceed the specified ratings. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. input/output equivalent circuits vcc pch r nch protective diode limiting resistance + b input (0 v to 16 v)
mb91350a series 82 2. recommended operating conditions (v ss = da vs = av ss = 0 v) warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 3.0 3.6 v at normal operating v cc 3.0 3.6 v hold ram status at stop analog power supply voltage da vc v ss ? 0.3 v ss + 3.6 v av cc v ss ? 0.3 v ss + 3.6 analog reference voltage avrh av ss av cc v operating temperature ta ? 40 + 85 c
mb91350a series 83 3. dc characteristics (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) (continued) parameter sym- bol pin conditions value unit remarks min typ max ?h? level input voltage v ih port 2, 3, 4, 5, 6, 9, a, b, c ? v cc 0.65 ? v cc ? 0.3 v v ihs port 8, g, h, i, m, n, o, p, md0, md1, md2, init , nmi ? v cc 0.8 ? v cc ? 0.3 v hysteresis input v ihst port j, k, l ? v cc 0.8 ? 5.25 v hysteresis input with stand voltage of 5 v ?l? level input voltage v il port 2, 3, 4, 5, 6, 9, a, b, c ? v ss ? v cc 0.25 v v ils port 8, g, h, i, m, n, o, p, md0, md1, md2, init , nmi ? v ss ? v cc 0.2 v hysteresis input v ilst port j, k, l ? v ss ? v cc 0.2 v hysteresis input with stand voltage of 5 v "h" level output voltage v oh port 2, 3, 4, 5, 6, 8, 9, a, b, c, g, h, i, j, k, m, n, o, p v cc = 3.0 v i oh = ? 4.0 ma v cc ? 0.5 ? v cc v ?l? level output voltage v ol1 port 2, 3, 4, 5, 6, 8, 9, a, b, c, g, h, i, j, k, m, n, o, p v cc = 3.0 v i ol = 4.0 ma v ss ? 0.4 v v ol2 port l v cc = 3.0 v i ol = 15.0 ma v ss ? 0.4 v nch open-drain input leak current (high-z output leak- age current) i li all input pin v cc = 3.6 v 0 mb91350a series 84 (continued) (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) parameter sym- bol pin conditions value unit remarks min typ max power supply current i cc v cc f c = 12.5 mhz v cc = 3.3 v ? 160 220 ma multiply by 4 clkb : 50 mhz clkt : 25 mhz when operating at 25 mhz i ccs f c = 12.5 mhz v cc = 3.3 v ? 100 140 ma sleep when operating at 25 mhz i cch ta = + 25 c v cc = 3.3 v ? 1100 aat stop i ccl ta = + 25 c f c = 32.768 khz v cc = 3.3 v ? 0.3 3.0 ma sub run clkb : 32.768 khz clkt : 32.768 khz when operating at 32.768 khz i ccls ta = + 25 c f c = 32.768 khz v cc = 3.3 v ? 0.2 2.0 ma sub sleep when operating at 32.768 khz i cct ta = + 25 c f c = 32.768 khz v cc = 3.3 v ? 5120 a at watch mode operating (main off, stop) input capacitance c ih other than v cc , v ss , av cc , av ss , da vc , da vs ?? 515pf
mb91350a series 85 4. ac characteristics (1) clock timing (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) * : the values assume a gear cycle of 1/16. parameter sym- bol pin conditions value unit remarks min typ max clock frequency f c x0 x1 ? 10 ? 12.5 mhz main pll (when operating at max internal frequency (50 mhz) = 12.5 mhz self-oscillation with 4 pll) clock cycle time t c x0 x1 80 ? 100 ns clock frequency f c x0 x1 ? 10 ? 25 mhz main self-oscillation (frequency-halved input) internal operating clock frequency f cp ? when a minimum value of 12.5 mhz is input as the x0 clock frequency and 4 multiplica- tion is set for the pll of the oscillator circuit 2.94* ? 50 mhz cpu f cpp 2.94* ? 25 mhz peripheral f cpt 2.94* ? 25 mhz external bus internal operating clock cycle time t cp ? 20 ? 340* ns cpu t cpp 40 ? 340* ns peripheral t cpt 40 ? 340* ns external bus clock frequency f c x0a x1a ? 30 32.768 35 khz sub self-oscillation clock cycle time t c x0a x1a ? 28.6 30.51 33.3 s internal operating clock frequency f cp , f cpp , f cpt ? when a standard value of 32.768 khz is input as the x0a clock frequency 2* ? 32 khz internal operating clock cycle time t cp , t cpp , t cpt ? 30.51 ? 500* s
mb91350a series 86 conditions for measuring the clock timing ratings operation assurance range 0.8 v cc 0.2 v cc t cf t cr t c p wh p wl c = 50 pf output pin 0 (mhz ) 3 .6 3 .0 f cp , f cp p 50 25 2.94 v cc (v) internal clock power supply operation assurance range (ta = ? 40 c to + 85 c ) f cpp is represented by the shaded area.
mb91350a series 87 external/internal clock setting range notes : ? when the pll is used, the external cl ock input must fall between 10.0 and 12.5 mhz. ? set the pll oscillation stabilization wait time longer than 454.5 s. the internal clock gear setting should not exceed the relevant value in the table in ?(1) clock timing ratings?. 50 (mhz) 25 12.5 4 : 4 2 : 2 1 : 2 f cp f cpp , f cpt internal clock cpu : cpu (clkb) : peripheral external bus(clkt) : oscillation input clock f c = 12.5 mhz
mb91350a series 88 (2)clock output timing (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) *1 : t cyc is the frequency of one clock cycle after gearing. *2 : the following ratings are for the gear ratio set to 1. for the ratings when the gea r ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation. (1 / 2 1 / n ) t cyc ? 10 *3 : the following rating are for the gear ratio set to 1. note : t cpt indicates the internal operating cl ock cycle time. see ?(1) clock timing?. in the following ac ratings, mclk is equivalent to sysclk. (3) reset and hardware standby ratings (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) note : t c indicates the clock cycle time. see ?(1) clock timing?. parameter symbol pin condi- tions value unit remarks min max cycle time t cyc mclk, sysclk ? t cpt ? ns *1 sysclk sysclk t chcl mclk, sysclk t cyc ? 5t cyc + 5ns*2 sysclk sysclk t clch mclk, sysclk t cyc ? 5t cyc + 5ns*3 parameter symbol pin condi- tions value unit remarks min max init input time (at power-on) t intl init ? t c 10 ? ns init input time (other than at power-on) t c 10 ns m clk s ysclk v oh v ol v oh t cyc t clch t chcl i nit 0.2 v cc t intl
mb91350a series 89 (4) normal bus access read/write operation (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) *1 : when the bus timing is delayed by automatic wait insertion or rdy input, add the time (t cyc the number of cycles added for the delay) to this rating. *2 : the following ratings are for the gear ratio set to 1. for the ratings when the gear ratio is set to between 1/2 to 1/16, substitute 1/2 to 1/16 for n in the following equation. calculation expression: 3/(2n) t cyc ? 15 *3 : awrxl : area wait register note : t cyc indicates the cycle time. see ?(2) clock output timing?. parameter symbol pin conditions value unit remarks min max cs0 to cs3 setup t cslch mclk, cs0 to cs3 awrxl* 3 : w02 = 03 ? ns t csdlch awr0l : w02 = 1 ? 3 ? ns cs0 to cs3 hold t chcsh ? 3t cyc /2 + 6ns address setup t asch mclk, a23 to a00 3 ? ns t aswl wr0 , wr1 , a23 to a00 3 ? ns t asrl rd , a23 to a00 3 ? ns address hold t chax mclk, a23 to a00 3t cyc /2 + 6ns t whax wr0 , wr1 , a23 to a00 ? 3 ? ns t rhax rd , a23 to a00 3 ? ns valid address valid data input time t avdv a23 to a00, d31 to d16 ? 3 / 2 t cyc ? 15 ns *1 *2 wr0 , wr1 delay time t chwl mclk, wr0 , wr1 ? 6ns wr0 , wr1 delay time t chwh ? 6ns wr0 , wr1 minimum pulse width t wlwh wr0 , wr1 t cyc ? 5 ? ns data setup wrx t dswh wr0 , wr1 , d31 to d16 t cyc ? ns wrx data hold time t whdx 3 ? ns rd delay time t chrl mclk, rd ? 6ns rd delay time t chrh ? 6ns rd valid data input time t rldv rd , d31 to d16 ? t cyc ? 10 ns *1 data setup rd time t dsrh 10 ? ns rd data hold time t rhdx 0 ? ns rd minimum pulse width t rlrh rd t cyc ? 5 ? ns as setup t aslch mclk, as 3 ? ns as hold t chash 3t cyc /2 + 6ns
mb91350a series 90 mclk cs0 to cs3 v oh v oh v oh v ol v ol v oh v oh v ol v oh v ol v ol v ol a23 to a00 rd d31 to d16 wr0, wr1 d31 to d16 v oh v oh v oh v oh v ol v oh v ol v oh v ol v oh t asch t avdv t rldv t dsrh t rhdx t wlwh t chwl t chwh t chax t chrh t dswh t whdx t cyc t chcsh t chrl t rlrh t cslch as (lba) v ol v oh t chash t aslch ba1 t asrl t rhax t aswl t whax write
mb91350a series 91 (5) multiplex bus access read/write operation (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) notes : ? this rating is not guaranteed when the cs rd /wr , and setup delay setting by awr: bit 1 is ?0?. ? beside this rating, normal bus interface ratings are applicable. ? t cyc indicates the cycle time. see ?(2) clock output timing?. parameter symbol pin condi- tions value unit remarks min max ad15 to ad0 address audi setup time mclk t asch mclk, d31 to d16 ? 3 ? ns mclk ad15 to ad0 address audi hold time t chax 3t cyc /2 + 6ns ad15 to ad0 address audi setup time as t asash as , d31 to d16 12 ? ns as ad15 to ad0 address audi hold time t ashax t cyc ? 3t cyc + 3ns mclk v oh v ol d31 to d16 v oh v oh v oh v oh v ol v oh t asch t chax t asash t ashax t cyc as v ol v oh ba1
mb91350a series 92 (6) ready input timings (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) parameter symbol pin conditions value unit remarks min max rdy setup time mclk t rdys mclk, rdy ? 15 ? ns mclk rdy hold time t rdyh mclk, rdy ? 0 ? ns m clk v oh v oh v ol v ol v ol v oh v ol v oh v oh v ol v oh v ol t rdyh t rdyh r dy r dy t cyc t rdys t rdys with wait without wait
mb91350a series 93 (7) hold timing (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) * : these are applied to only the case that sren bi t of area select register (acr) is set to ?1?. notes : ? it takes 1 cycle or more from when brq is captured until bgrnt changes. ? t cyc indicates the cycle time. see ?(2) clock output timing?. parameter symbol pin conditions value unit remarks min max brq setup time mclk t brqs mclk, brq ? 15 ? ns mclk brq audi hold time t brqh 0 ? ns bgrnt delay time t chbgl mclk, bgrnt ? t cyc /2 ? 6t cyc /2 + 6ns bgrnt delay time t chbgh t cyc /2 ? 6 t cyc /2 + 6 ns pin floating bgrnt time t xzbgl bgrnt , d31 to d16, a23 to a00, cs3 to cs0 * t cyc ? 10 t cyc + 10 ns bgrnt pin valid time t bghxv t cyc ? 10 t cyc + 10 ns mclk v oh t chbgl v ol v oh v oh v ol v oh v oh v oh t chbgh brq bgrnt t cyc t bghxv t xzbgl t brqs t brqh d 31 to d16, a 23 to a00, c s3 to cs0 * high-z * : these are applied to only the case that sren bit of area select register (acr) is set to ?1?.
mb91350a series 94 (8) uart, sio timing (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) notes : ? above rating is for clk synchronous mode. ? t cpp indicates the peripheral clock cycle time. see ?(1) clock timing?. parameter symbol pin conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck7 internal shift clock mode 8 t cpp ? ns sck bgrnt delay time t slov sck0 to sck7, so0 to so7 ? 80 + 80 ns valid si sck t ivsh sck0 to sck7, si0 to si7 100 ? ns sck valid sin hold time t shix sck0 to sck7, si0 to si7 60 ? ns serial clock h pulse width t shsl sck0 to sck7 external shift clock mode 4 t cpp ? ns serial clock l pulse width t slsh sck0 to sck7 4 t cpp ? ns sck so delay time t slov sck0 to sck7, so0 to so7 ? 150 ns valid si sck t ivsh sck0 to sck7, si0 to si7 60 ? ns sck valid si hold time t shix sck0 to sck7, si0 to si7 60 ? ns internal shift clock mode external shift clock mode s ck0 to sck7 s o0 to so7 s i0 to si7 t scyc t slov t ivsh t shix v ol v oh v ol v oh v ol v oh v ol v oh v ol s ck0 to sck7 s o0 to so7 s i0 to si7 t slov t slsh t shsl t ivsh t shix v oh v ol v oh v ol v ol v ol v oh v ol v oh v ol
mb91350a series 95 (9) free-run timer clock, ppg timer input timing (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) note : t cpp indicates the peripheral clock cycle time. see ?(1) clock timing?. (10) trigger input timing (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) note : t cpp indicates the peripheral clock cycle time. see ?(1) clock timing?. parameter symbol pin conditions value unit remarks min max input pulse width t tiwh t tiwl frck, trg0 to trg5, ain0 to ain1, bin0 to bin1, zin0 to zin1 ? 2 t cpp ? ns parameter symbol pin conditions value unit remarks min max a/d activation trigger input time t atgx atg ? 5 t cpp ? ns input capture input trigger t inp in0 to in3 ? 5 t cpp ? ns t tiwh t tiwl a tg, i n0 to in3 t atgx , t inp
mb91350a series 96 (11)dma controller timing ? for edge detection (block/step transfer mode,burst transfer mode) (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) * : t cyc becomes t cp when f cpt is greater than f cp . for level detection (d emand transfer mode) (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) common operation mode (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) * : awrxl: area wait register. note : t cyc indicates the cycle time. see ?(2) clock output timing?. parameter symbol pin conditions value unit remarks min max dreq input pulse width t drwl dreq 0 to dreq2 ? 2 t cyc * ? ns dreq input pulse width t dswh dstp 0 to dstp2 2 t cyc * ? ns parameter symbol pin condi- tions value unit remarks min max dreq setup time t drs mclk, dreq 0 to dreq2 ? 15 ? ns dreq hold time t drh mclk, dreq 0 to dreq2 0.0 ? ns dstp setup time t dstps mclk, dstp 0 to dstp2 15 ? ns dstp hold time t dstph mclk,dstp 0 to dstp2 0.0 ? ns parameter symbol pin condi- tions value unit remarks min max dack delay time t dalch mclk, dack 0 to dack2 awrxl* : w02 = 0 3 ? ns cs timing ? 6 ns fr30 compatible t dadlch awr0l : w02 = 1 ? 3 ? ns cs timing ? 6 ns fr30 compatible t chdah ? ? t cyc /2 + 6 ns cs timing ? 6 ns fr30 compatible deop delay time t delch mclk, deop 0 to deop2 awr0l : w02 = 0 3 ? ns cs timing ? 6 ns fr30 compatible t dedlch awrxl* : w02 = 1 ? 3 ? ns cs timing ? 6 ns fr30 compatible t chdeh ? ? t cyc /2 + 6 ns cs timing ? 6 ns fr30 compatible iord delay time t chirl mclk, iord ? ? 6ns t chirh ? 6ns iowr delay time t chiwl mclk, iowr ? 6ns t chiwh ? 6ns iord minimum pulse width t irlirh iord 12 ? ns iowr minimum pulse width t iwliwh iowr 12 ? ns
mb91350a series 97 m clk d ack0 to dack2 d ack0 to dack2 d req0 to dreq2 d stp0 to dstp2 i ord v ol v oh v ol v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh t dalch t dadlch t chirl t chiwl t irlirh t iwliwh t dalch t dadlch t cyc t chirh t chiwh t drs t drh t dstps t dstph t drwl t dswh t chdah d eop0 to deop2 v ol v oh t delch t dedlch t chdeh i owr r d, w rn d eop0 to deop2 v ol v oh t delch t dedlch t chdah t chdeh chip select timing fr30 compatible timing
mb91350a series 98 (12) i 2 c timing (v cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, ta = ? 40 c to + 85 c) *1 : r,c : pull-up resistor and lo ad capacitor of the scl and sda lines. *2 : the maximum t hddat only has to be met if the device does not stretch the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must then be met. *4 : for use at over 100 khz, set t he machine clock to at least 6 mhz. parameter symbol condition standard-mode fast-mode* 4 unit min max min max scl clock frequency* 4 f scl r = 1.0 k ? , c = 50 pf* 1 0 100 0 400 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? 0.6 ? s ?l? width of the scl clock t low 4.7 ? 1.3 ? s ?h? width of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s data hold time scl sda t hddat 0 3.45* 2 00.9* 3 s data set-up time sda scl t sudat 250 ? 100 ? ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? s bus free time between a stop and start condition t bus 4.7 ? 1.3 ? s s da s cl t low t sudat t hdsta t bus t hdsta t hddat t high t susta t susto
mb91350a series 99 5. electrical characteristics for the a/d converter (v cc = av cc = 3.0 v to 3.6 v, v ss = da vs = av ss = 0 v, avrh = 3.0 v to 3.6 v, ta = ? 40 c to + 85 c) *1: measured in the cpu sleep state *2: when the peripheral resource clock frequency is 25.0 mhz, set the conversion time setting register (adct) to a value equal to or greater than 5334 h . set each bit as follow : sampling time : samp3 to samp0 5 h conversion time a : cv03 to cv0 3 h conversion time b : cv13 to cv0 3 h conversion time c : cv23 to cv0 4 h parameter symbol pin value unit remarks min typ max resolution ?? ? ? 10 bit total error* 1 ?? ? 5.0 ? + 5.0 lsb avcc = 3.3 v, avrh = 3.3 v nonlinear error* 1 ?? ? 3.5 ? + 3.5 lsb differential linear error* 1 ?? ? 2.5 ? + 2.5 lsb zero transition voltage* 1 ? an11 to an0 avrl ? 2.0 avrl + 1.0 avrl + 6.0 lsb full-transition voltage* 1 ? an11 to an0 avrh ? 5.5 avrh + 1.5 avrh + 3.0 lsb conversion time ?? 1.48* 2 ? 300 s analog power supply current (analog + digital) i a av cc ? 8 ? ma i ah ?? 5 aat stop reference power supply current (between avrh and avrl) i r avrh ? 470 ? a avrh = 3.0 v, avrl = 0.0 v i rh ?? 10 aat stop analog input capacitance ? an11 to an0 ? 40 ? pf interchannel disparity ? an11 to an0 ?? 4lsb
mb91350a series 100 ? about the external impedance of th e analog input and its sampling time ? a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. to satisfy the a/d conversion precision standard, co nsider the relationship between the external impedance and minimum sampling time and either adjust the resi stor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. if the sampling time cannot be suffici ent, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |avrh-av ss | becomes smaller, values of relative errors grow larger. r c analog input comparator ? analog input circuit model during sampling : on note : the values are reference values. mb91355a MB91F355A r 0.18 k ? (max) 0.18 k ? (max) c 63.0 pf (max) 39.0 pf (max) 1 00 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 3 5 MB91F355A mb91355a 2 0 1 8 1 6 1 4 1 2 1 0 8 6 4 2 0 0123456 8 7 MB91F355A mb91355a (external impedance = 0 k ? to 100 k ? ) external impedance [k ? ] minimum sampling time [ s] (external impedance = 0 k ? to 20 k ? ) external impedance [k ? ] minimum sampling time [ s] ? the relationship between the exter nal impedance and minimum sampling time
mb91350a series 101 definition of a/d converter terms resolution analog variation that is recognized by an a/d converter. linearity error zero transition point ( "0000000000? - ?0 000000001?) and full-scale transition point difference between the line connect ed (?1111111110? - ?1111111111?) and ac tual conversion characteristics. differential linear error deviation of input voltage, which is required for ch anging output code by 1 lsb, from an ideal value. v nt : a voltage at which digital output transitions from (n - 1) to n. linear error in digital output n = v nt ? {1 lsb? (n ? 1) + {v ot } 1 lsb? [lsb] differential linear error in digital output n = v (n + 1) t ? v nt 1 lsb? ? 1 [lsb] 1 lsb = v fst ? v ot 1022 [v] v fst : a voltage at which digital output transitions from (3fe) h to (3ff) h . 3ff h 3fe h 3 fd h 004 h 003 h 002 h 001 h av ss avr h {1 lsb' (n ? 1) + v ot } n ? 1 av ss avr h n ? 2 n n + 1 linearity error differential linear error digital output digital output actual conversion characteristic v fst (measure- ment value) v nt (measurement value) actual conversion characteristic ideal characteristics v ot (measurement value) analog input analog input ideal characteristics actual conversion characteristic v (n+1)t (measurement value) v nt (measurement value) actual conversion characteristic v ot : a voltage at which digital output transitions from (000) h to (001) h .
mb91350a series 102 total error this error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error. 3 ff h 3 fe h 3 fd h 004 h 003 h 002 h 001 h av ss avrh 1.5 ls b' 0.5 lsb' {1 lsb' (n ? 1) + 0.5 lsb'} total error digital output actual conversion characteristic v nt (measurement value) analog input total error of digital output n = v nt ? {1 lsb? (n ? 1) {0.5 lsb?} 1 lsb? v ot ?(ideal value) = av ss + {0.5 lsb? [v] v fst ?(ideal value) = avrh ? 1.5 lsb? [v] v nt : a voltage at which digital output transitions from (n + 1) to (n). 1ls? (ideal value) 1 = avrh ? av ss 1024 [v] actual characteristics ideal characteristics
mb91350a series 103 6. electrical characteristics for the d/a converter (v cc = da vc = 3.0 v = 3.6 v, v ss = da vs = 0 v, ta = ? 40 c to + 85 c) * : this d/a converter varies in current co nsumption depending on each input digital code. this rating indicates the current consumption when the di gital code that maximizes current consumption is input. parameter symbol pin value unit remarks min typ max resolution ???? 8bit nonlinear error ?? ? 2.0 ? + 2.0 lsb when the output is unloaded differential linear error ?? ? 1.0 ? + 1.0 lsb when the output is unloaded convertion speed ??? 0.6 ? s when load capacitance (c l ) = 20 pf ??? 3.0 ? s when load capacitance (c l ) = 100 pf output high impedance ? da0 to da2 2.0 2.9 3.8 k ? analog current ? da vc ? 40 ? a 10 s conversion when the output is unloaded i ada ?? 460* a input digital code when fixed at 7a h or 85 h i adah ? 0.1 ? a at power-down
mb91350a series 104 flash memory write/erase characteristics *: this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c). parameter condition value unit remarks min typ max sector erase time ta = + 25 c, v cc = 3.3 v ? 115s excludes 00 h programming prior erasure. chip erase time ? 8 ? s excludes 00 h programming prior erasure. half word (16-bit width) writing time ? 16 3,600 s excludes system-level overhead. write/erase cycle ?? 10,000 ? cycle flash data retention time average ta = + 85 c 20 ?? year *
mb91350a series 105 example characteristics (continued) (1) ?h? level output voltage (2) ?l? level output voltage (3) ?l? level output voltage (nch open-drain) (4) input leak current (5) pull-up resistance 4 3 2 1 0 2.7 3.0 3.3 3.6 3 .9 v oh [v] v cc [v] v oh - v cc ta = +25 c v ol1 [mv] v cc [v] 2.7 3.0 3.3 3.6 3 .9 0 100 200 300 400 500 v ol1 - v cc ta = +25 c v ol2 [mv] v cc [v] 2.7 3.0 3.3 3.6 3 .9 0 100 200 300 400 500 v ol2 - v cc ta = +25 c 2.7 3.0 3.3 3.6 3 .9 ? 6 ? 4 ? 2 0 2 4 6 i li [ a] v cc [v] i li - v cc ta = +25 c 2.7 3.0 3.3 3.6 3 .9 v cc [v] r up [k ? ] 200 160 120 80 40 0 r up - v cc ta = +25 c
mb91350a series 106 (continued) (6) power supply current (7) power supply current (8) power supply current at sleep (9) power supply current at sleep (10) power supply current at stop (11) sub run power supply current (12) sub sleep power s upply current (13) watch mode power supply current i cc [ma] v cc [v] 2.7 3.0 3.3 3.6 3 .9 300 250 200 150 100 50 0 i cc - v cc ta = +25 c, f cp = 50 mhz, f ccp = f cpt = 25 mhz 1 10 100 300 250 200 150 100 50 0 i cc [ma] f c [mhz] i cc - f c ta = +25 = = i ccs [ma] v cc [v] 2.7 3.0 3.3 3.6 3 .9 300 250 200 150 100 50 0 i ccs - v cc ta = +25 c, f cp = 50 mhz, f ccp = f cpt = 25 mhz 1 10 100 300 250 200 150 100 50 0 i ccs [ma] f c [mhz] i ccs - f c ta = +25 = = v cc [v] 2.7 3.0 3.3 3.6 3 .9 i cch [ a] ? 20 0 20 40 60 80 100 i cch - v cc ta = +25 c v cc [v] 2.7 3.0 3.3 3.6 3 .9 i ccl [ a] 0 100 200 300 400 500 i ccl - v cc ta = +25 c, f cp = 32 khz , f ccp = f cpt = 32 khz 500 400 300 200 100 0 2.7 3.0 3.3 3.6 3 .9 i ccls [ a] v cc [v] i ccls - v cc ta = +25 c, f cp = 32 khz, f ccp = f cpt = 32 khz v cc [v] i cct [ a] 100 80 60 40 20 0 ? 20 2.7 3.0 3.3 3.6 3 .9 i cct - v cc ta = +25 c, f cp = 32 khz, f ccp = f cpt = 32 khz
mb91350a series 107 (continued) (14) a/d converter power supply current ( 15) a/d converter reference power supply voltage (16) a/d converter power supply current at stop (17) a/d converter reference power supply current at stop (18) d/a converter power supply current < per 1 channel > (19) d/a converter power supply current at power down 10 8 6 4 2 0 2.7 3.0 3.3 3.6 3 .9 i a [ma] v cc [v] i a - v cc ta = +25 c 1000 800 600 400 200 0 2.7 3.0 3.3 3.6 3.9 i r [ = + ? = + ? = + = + ? = +
mb91350a series 108 ordering information part number package remarks MB91F355Apmt-002 176-pin plastic lqfp (fpt-176p-m02) lead-free package mb91355apmt 176-pin plastic lqfp (fpt-176p-m02) lead-free package mb91354apmt 176-pin plastic lqfp (fpt-176p-m02) lead-free package
mb91350a series 109 package dimension 176-pin plastic lqfp (fpt-176p-m02) note 1) * : values do not include resin protrusion. resin protrusion is + 0.25 (.010) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches). note: the values in parentheses are reference values. c 2003 fujitsu limited f176006s-c-4-6 details of "a" part 0 ? ~8 ? 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) (stand off) (.004.004 ) 0.100.10 1.50 +0.20 ?0.10 +.008 ?.004 .059 (mounting height) 0.08(.003) (.006.002) 0.1450.055 "a" index 1 lead no. 44 45 88 89 132 133 176 0.50(.020) 0.220.05 (.009.002) m 0.08(.003) 24.000.10(.945.004)sq 26.000.20(1.024.008)sq *
mb91350a series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0411 ? 2004 fujitsu limited printed in japan

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